Lines Matching defs:reloc
190 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
195 * @reloc: reloc informations
235 * evergreen_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
263 * RELOC (P3) - crtc_id in reloc.
361 DRM_ERROR("unknown crtc reloc\n");
380 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
424 struct radeon_cs_reloc *reloc;
475 r = evergreen_cs_packet_next_reloc(p, &reloc);
484 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
503 r = evergreen_cs_packet_next_reloc(p, &reloc);
510 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
511 track->db_z_read_bo = reloc->robj;
514 r = evergreen_cs_packet_next_reloc(p, &reloc);
521 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
522 track->db_z_write_bo = reloc->robj;
525 r = evergreen_cs_packet_next_reloc(p, &reloc);
532 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
533 track->db_s_read_bo = reloc->robj;
536 r = evergreen_cs_packet_next_reloc(p, &reloc);
543 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
544 track->db_s_write_bo = reloc->robj;
588 r = evergreen_cs_packet_next_reloc(p, &reloc);
596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
599 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
608 r = evergreen_cs_packet_next_reloc(p, &reloc);
616 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
619 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
706 r = evergreen_cs_packet_next_reloc(p, &reloc);
711 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
712 track->cb_color_fmask_bo[tmp] = reloc->robj;
723 r = evergreen_cs_packet_next_reloc(p, &reloc);
728 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
729 track->cb_color_cmask_bo[tmp] = reloc->robj;
761 r = evergreen_cs_packet_next_reloc(p, &reloc);
769 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
771 track->cb_color_bo[tmp] = reloc->robj;
777 r = evergreen_cs_packet_next_reloc(p, &reloc);
785 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
787 track->cb_color_bo[tmp] = reloc->robj;
891 r = evergreen_cs_packet_next_reloc(p, &reloc);
897 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
926 struct radeon_cs_reloc *reloc;
960 r = evergreen_cs_packet_next_reloc(p, &reloc);
965 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
966 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
978 r = evergreen_cs_packet_next_reloc(p, &reloc);
983 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
984 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
996 r = evergreen_cs_packet_next_reloc(p, &reloc);
1001 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1002 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1071 r = evergreen_cs_packet_next_reloc(p, &reloc);
1076 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1077 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1088 r = evergreen_cs_packet_next_reloc(p, &reloc);
1093 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1102 r = evergreen_cs_packet_next_reloc(p, &reloc);
1107 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1108 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1116 r = evergreen_cs_packet_next_reloc(p, &reloc);
1121 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1122 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1129 r = evergreen_cs_packet_next_reloc(p, &reloc);
1134 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1135 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1189 r = evergreen_cs_packet_next_reloc(p, &reloc);
1194 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1195 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1197 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1199 texture = reloc->robj;
1201 r = evergreen_cs_packet_next_reloc(p, &reloc);
1206 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1207 mipmap = reloc->robj;
1215 r = evergreen_cs_packet_next_reloc(p, &reloc);
1222 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1225 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1227 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1228 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;