Lines Matching defs:ib
143 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
148 * if packet is bigger than remaining ib size. or if packets is unknown.
279 volatile uint32_t *ib;
281 ib = p->ib->ptr;
345 ib[h_idx + 2] = PACKET2(0);
346 ib[h_idx + 3] = PACKET2(0);
347 ib[h_idx + 4] = PACKET2(0);
348 ib[h_idx + 5] = PACKET2(0);
349 ib[h_idx + 6] = PACKET2(0);
350 ib[h_idx + 7] = PACKET2(0);
351 ib[h_idx + 8] = PACKET2(0);
357 ib[h_idx] = header;
358 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
380 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
426 u32 m, i, tmp, *ib;
437 ib = p->ib->ptr;
469 ib[idx] = 0;
482 ib[idx] &= ~Z_ARRAY_MODE(0xf);
485 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
488 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
510 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
521 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
532 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
543 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
597 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
600 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
617 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
620 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
711 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
728 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
769 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
770 track->cb_color_base_last[tmp] = ib[idx];
785 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
786 track->cb_color_base_last[tmp] = ib[idx];
897 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
928 volatile u32 *ib;
936 ib = p->ib->ptr;
965 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
966 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
983 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
984 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1001 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1002 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1076 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1077 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1093 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1107 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1108 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1121 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1122 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1134 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1135 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1194 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1196 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
1198 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
1206 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1225 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1227 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1228 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;