Lines Matching refs:dev_priv
49 drm_r128_private_t *dev_priv = dev->dev_private;
56 static void r128_status(drm_r128_private_t *dev_priv)
77 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv)
85 for (i = 0; i < dev_priv->usec_timeout; i++) {
97 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries)
101 for (i = 0; i < dev_priv->usec_timeout; i++) {
114 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv)
118 ret = r128_do_wait_for_fifo(dev_priv, 64);
122 for (i = 0; i < dev_priv->usec_timeout; i++) {
124 r128_do_pixcache_flush(dev_priv);
141 static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
171 r128_do_wait_for_idle(dev_priv);
191 static void r128_do_cce_flush(drm_r128_private_t *dev_priv)
201 int r128_do_cce_idle(drm_r128_private_t *dev_priv)
205 for (i = 0; i < dev_priv->usec_timeout; i++) {
206 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
209 dev_priv->cce_fifo_size) &&
212 return r128_do_pixcache_flush(dev_priv);
220 r128_status(dev_priv);
227 static void r128_do_cce_start(drm_r128_private_t *dev_priv)
229 r128_do_wait_for_idle(dev_priv);
232 dev_priv->cce_mode | dev_priv->ring.size_l2qw
237 dev_priv->cce_running = 1;
244 static void r128_do_cce_reset(drm_r128_private_t *dev_priv)
248 dev_priv->ring.tail = 0;
255 static void r128_do_cce_stop(drm_r128_private_t *dev_priv)
261 dev_priv->cce_running = 0;
268 drm_r128_private_t *dev_priv = dev->dev_private;
271 r128_do_pixcache_flush(dev_priv);
292 r128_do_cce_reset(dev_priv);
295 dev_priv->cce_running = 0;
304 drm_r128_private_t *dev_priv)
315 if (!dev_priv->is_pci)
316 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
319 ring_start = dev_priv->cce_ring->offset -
344 drm_r128_private_t *dev_priv;
354 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
355 if (dev_priv == NULL)
358 dev_priv->is_pci = init->is_pci;
360 if (dev_priv->is_pci && !dev->sg) {
362 dev->dev_private = (void *)dev_priv;
367 dev_priv->usec_timeout = init->usec_timeout;
368 if (dev_priv->usec_timeout < 1 ||
369 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
371 dev->dev_private = (void *)dev_priv;
376 dev_priv->cce_mode = init->cce_mode;
380 atomic_set(&dev_priv->idle_count, 0);
391 dev->dev_private = (void *)dev_priv;
398 dev_priv->cce_fifo_size = 0;
402 dev_priv->cce_fifo_size = 192;
406 dev_priv->cce_fifo_size = 128;
413 dev_priv->cce_fifo_size = 64;
419 dev_priv->color_fmt = R128_DATATYPE_RGB565;
423 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
426 dev_priv->front_offset = init->front_offset;
427 dev_priv->front_pitch = init->front_pitch;
428 dev_priv->back_offset = init->back_offset;
429 dev_priv->back_pitch = init->back_pitch;
433 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
438 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
441 dev_priv->depth_offset = init->depth_offset;
442 dev_priv->depth_pitch = init->depth_pitch;
443 dev_priv->span_offset = init->span_offset;
445 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
446 (dev_priv->front_offset >> 5));
447 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
448 (dev_priv->back_offset >> 5));
449 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
450 (dev_priv->depth_offset >> 5) |
452 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
453 (dev_priv->span_offset >> 5));
455 dev_priv->sarea = drm_getsarea(dev);
456 if (!dev_priv->sarea) {
458 dev->dev_private = (void *)dev_priv;
463 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
464 if (!dev_priv->mmio) {
466 dev->dev_private = (void *)dev_priv;
470 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
471 if (!dev_priv->cce_ring) {
473 dev->dev_private = (void *)dev_priv;
477 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
478 if (!dev_priv->ring_rptr) {
480 dev->dev_private = (void *)dev_priv;
488 dev->dev_private = (void *)dev_priv;
493 if (!dev_priv->is_pci) {
494 dev_priv->agp_textures =
496 if (!dev_priv->agp_textures) {
498 dev->dev_private = (void *)dev_priv;
504 dev_priv->sarea_priv =
505 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
509 if (!dev_priv->is_pci) {
510 drm_core_ioremap_wc(dev_priv->cce_ring, dev);
511 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
513 if (!dev_priv->cce_ring->handle ||
514 !dev_priv->ring_rptr->handle ||
517 dev->dev_private = (void *)dev_priv;
524 dev_priv->cce_ring->handle =
525 (void *)(unsigned long)dev_priv->cce_ring->offset;
526 dev_priv->ring_rptr->handle =
527 (void *)(unsigned long)dev_priv->ring_rptr->offset;
533 if (!dev_priv->is_pci)
534 dev_priv->cce_buffers_offset = dev->agp->base;
537 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
539 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
540 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
542 dev_priv->ring.size = init->ring_size;
543 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
545 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
547 dev_priv->ring.high_mark = 128;
549 dev_priv->sarea_priv->last_frame = 0;
550 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
552 dev_priv->sarea_priv->last_dispatch = 0;
553 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
556 if (dev_priv->is_pci) {
558 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
559 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
560 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
561 dev_priv->gart_info.addr = NULL;
562 dev_priv->gart_info.bus_addr = 0;
563 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
564 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
566 dev->dev_private = (void *)dev_priv;
570 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
575 r128_cce_init_ring_buffer(dev, dev_priv);
576 rc = r128_cce_load_microcode(dev_priv);
578 dev->dev_private = (void *)dev_priv;
601 drm_r128_private_t *dev_priv = dev->dev_private;
604 if (!dev_priv->is_pci) {
605 if (dev_priv->cce_ring != NULL)
606 drm_core_ioremapfree(dev_priv->cce_ring, dev);
607 if (dev_priv->ring_rptr != NULL)
608 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
616 if (dev_priv->gart_info.bus_addr)
618 &dev_priv->gart_info))
650 drm_r128_private_t *dev_priv = dev->dev_private;
655 DEV_INIT_TEST_WITH_RETURN(dev_priv);
657 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
662 r128_do_cce_start(dev_priv);
672 drm_r128_private_t *dev_priv = dev->dev_private;
679 DEV_INIT_TEST_WITH_RETURN(dev_priv);
685 r128_do_cce_flush(dev_priv);
691 ret = r128_do_cce_idle(dev_priv);
700 r128_do_cce_stop(dev_priv);
712 drm_r128_private_t *dev_priv = dev->dev_private;
717 DEV_INIT_TEST_WITH_RETURN(dev_priv);
719 r128_do_cce_reset(dev_priv);
722 dev_priv->cce_running = 0;
729 drm_r128_private_t *dev_priv = dev->dev_private;
734 DEV_INIT_TEST_WITH_RETURN(dev_priv);
736 if (dev_priv->cce_running)
737 r128_do_cce_flush(dev_priv);
739 return r128_do_cce_idle(dev_priv);
768 drm_r128_private_t *dev_priv = dev->dev_private;
781 for (t = 0; t < dev_priv->usec_timeout; t++) {
818 int r128_wait_ring(drm_r128_private_t *dev_priv, int n)
820 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
823 for (i = 0; i < dev_priv->usec_timeout; i++) {
824 r128_update_ring_snapshot(dev_priv);