Lines Matching refs:dev_priv
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
79 if (dev_priv->card_type < NV_C0)
83 dev_priv->engine.instmem.flush(dev);
91 struct drm_nouveau_private *dev_priv = dev->dev_private;
131 if (dev_priv->chipset != 0x50) {
149 0, dev_priv->vram_size);
197 struct drm_nouveau_private *dev_priv = dev->dev_private;
198 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
199 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
200 struct nouveau_channel *evo = dev_priv->evo;
249 ram_amount = dev_priv->vram_size;
397 struct drm_nouveau_private *dev_priv = dev->dev_private;
409 ret = RING_SPACE(dev_priv->evo, 2);
411 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
412 OUT_RING(dev_priv->evo, 0);
414 FIRE_RING(dev_priv->evo);
458 if (dev_priv->chipset >= 0x90) {
467 struct drm_nouveau_private *dev_priv = dev->dev_private;
468 struct dcb_table *dcb = &dev_priv->vbios.dcb;
489 dev->mode_config.fb_base = dev_priv->fb_phys;
492 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
552 struct drm_nouveau_private *dev_priv = dev->dev_private;
559 nv50_evo_channel_del(&dev_priv->evo);
566 struct drm_nouveau_private *dev_priv = dev->dev_private;
569 struct nvbios *bios = &dev_priv->vbios;
642 struct drm_nouveau_private *dev_priv = dev->dev_private;
646 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
674 struct drm_nouveau_private *dev_priv = dev->dev_private;
679 dev_priv->evo_irq.dcb = NULL;
714 if (dev_priv->chipset < 0x90 ||
715 dev_priv->chipset == 0x92 ||
716 dev_priv->chipset == 0xa0)
745 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
746 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
750 dev_priv->evo_irq.dcb = dcb;
795 struct drm_nouveau_private *dev_priv = dev->dev_private;
801 dcb = dev_priv->evo_irq.dcb;
804 dev_priv->evo_irq.dcb = NULL;
845 if (dev_priv->chipset < 0x90 ||
846 dev_priv->chipset == 0x92 ||
847 dev_priv->chipset == 0xa0)
875 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
876 dcb = &dev_priv->vbios.dcb.entry[i];
881 if (i == dev_priv->vbios.dcb.entries) {
901 dev_priv->evo_irq.dcb = dcb;
902 dev_priv->evo_irq.pclk = pclk;
903 dev_priv->evo_irq.script = script;
944 struct drm_nouveau_private *dev_priv = dev->dev_private;
945 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
946 u16 script = dev_priv->evo_irq.script;
947 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
950 dev_priv->evo_irq.dcb = NULL;
966 struct drm_nouveau_private *dev_priv =
968 struct drm_device *dev = dev_priv->dev;
1009 struct drm_nouveau_private *dev_priv =
1011 struct drm_device *dev = dev_priv->dev;
1017 spin_lock_irq(&dev_priv->hpd_state.lock);
1018 hpd0 = dev_priv->hpd_state.hpd0_bits;
1019 dev_priv->hpd_state.hpd0_bits = 0;
1020 hpd1 = dev_priv->hpd_state.hpd1_bits;
1021 dev_priv->hpd_state.hpd1_bits = 0;
1022 spin_unlock_irq(&dev_priv->hpd_state.lock);
1025 if (dev_priv->chipset >= 0x90)
1074 struct drm_nouveau_private *dev_priv = dev->dev_private;
1083 if (dev_priv->chipset >= 0x90) {
1088 spin_lock(&dev_priv->hpd_state.lock);
1089 dev_priv->hpd_state.hpd0_bits |= hpd0_bits;
1090 dev_priv->hpd_state.hpd1_bits |= hpd1_bits;
1091 spin_unlock(&dev_priv->hpd_state.lock);
1093 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1121 if (!work_pending(&dev_priv->irq_work))
1122 queue_work(dev_priv->wq, &dev_priv->irq_work);