Lines Matching refs:dev_priv
31 #define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV40_RAMFC__SIZE))
38 struct drm_nouveau_private *dev_priv = dev->dev_private;
49 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
68 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
87 struct drm_nouveau_private *dev_priv = dev->dev_private;
153 struct drm_nouveau_private *dev_priv = dev->dev_private;
154 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
159 if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
236 struct drm_nouveau_private *dev_priv = dev->dev_private;
239 ((dev_priv->ramht_bits - 9) << 16) |
240 (dev_priv->ramht_offset >> 8));
241 nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
243 switch (dev_priv->chipset) {
253 switch (dev_priv->chipset) {
268 ((dev_priv->vram_size - 512 * 1024 +
269 dev_priv->ramfc_offset) >> 16) | (3 << 16));
284 struct drm_nouveau_private *dev_priv = dev->dev_private;
285 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
298 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
299 if (dev_priv->fifos[i]) {