Lines Matching refs:dev_priv
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 if (dev_priv->chipset >= 0x40)
14 if (dev_priv->chipset >= 0x17)
23 struct drm_nouveau_private *dev_priv = dev->dev_private;
27 if (dev_priv->card_type >= NV_40) {
33 switch (dev_priv->chipset) {
38 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
41 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
45 dev_priv->ramin_rsvd_vram = (512 * 1024);
47 NV_DEBUG(dev, "RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram >> 10);
50 for (i = 64 * 1024; i < dev_priv->ramin_rsvd_vram; i += 4)
57 struct drm_nouveau_private *dev_priv = dev->dev_private;
58 struct nouveau_engine *engine = &dev_priv->engine;
64 dev_priv->ramht_offset = 0x10000;
65 dev_priv->ramht_bits = 9;
66 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */
67 dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */
68 NV_DEBUG(dev, "RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
69 dev_priv->ramht_size);
72 dev_priv->ramro_offset = 0x11200;
73 dev_priv->ramro_size = 512;
74 NV_DEBUG(dev, "RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
75 dev_priv->ramro_size);
83 dev_priv->ramfc_size = engine->fifo.channels *
85 switch (dev_priv->card_type) {
87 dev_priv->ramfc_offset = 0x20000;
94 dev_priv->ramfc_offset = 0x11400;
97 NV_DEBUG(dev, "RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
98 dev_priv->ramfc_size);
103 struct drm_nouveau_private *dev_priv = dev->dev_private;
113 offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
123 if (dev_priv->card_type >= NV_40) {
128 ret = drm_mm_init(&dev_priv->ramin_heap, offset,
129 dev_priv->ramin_rsvd_vram - offset);
155 struct drm_nouveau_private *dev_priv = dev->dev_private;
159 dev_priv->engine.instmem.unbind(dev, gpuobj);