Lines Matching refs:dev_priv
92 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
112 struct drm_nouveau_private *dev_priv = dev->dev_private;
119 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
134 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
203 struct nv04_mode_state *state = &dev_priv->mode_reg;
233 if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
234 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
246 struct drm_nouveau_private *dev_priv = dev->dev_private;
248 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
287 struct drm_nouveau_private *dev_priv = dev->dev_private;
289 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
290 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
304 dev_priv->vbios.digital_min_front_porch)
307 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
413 if (dev_priv->chipset == 0x11)
424 if (dev_priv->chipset != 0x11) {
441 struct drm_nouveau_private *dev_priv = dev->dev_private;
456 dev_priv->mode_reg.crtc_reg[head].fp_control =
460 if (dev_priv->chipset < 0x44)
508 struct drm_nouveau_private *dev_priv = dev->dev_private;
552 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
553 dev_priv->mode_reg.sel_clk &= ~0xf0;
555 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
588 struct drm_nouveau_private *dev_priv = dev->dev_private;
601 (&dev_priv->saved_reg.crtc_reg[head].pllvals);