Lines Matching defs:output_mode
293 struct drm_display_mode *output_mode = &nv_encoder->mode;
297 drm_mode_debug_printmodeline(output_mode);
300 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
301 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
303 (output_mode->hsync_start - output_mode->hdisplay) >=
305 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
307 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
308 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
309 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
310 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
311 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
313 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
314 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
315 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
316 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
317 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
319 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
326 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
328 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
334 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
335 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
342 output_mode->clock > 165000)
352 if (output_mode->clock > 165000)
370 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
383 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
388 diff = output_mode->hdisplay -
389 output_mode->vdisplay * mode_ratio / (1 << 12);
399 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
404 diff = output_mode->vdisplay -
405 (1 << 12) * output_mode->hdisplay / mode_ratio;