Lines Matching refs:regp
52 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
54 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
56 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
57 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
58 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
60 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
67 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
72 regp->ramdac_634 = level;
73 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
108 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
109 struct nouveau_pll_vals *pv = ®p->pllvals;
234 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
282 regp->MiscOutReg = 0x23;
284 regp->MiscOutReg |= 0x40;
286 regp->MiscOutReg |= 0x80;
294 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
296 regp->MiscOutReg = 0x63; /* -hsync +vsync */
298 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
300 regp->MiscOutReg = 0x23; /* +hsync +vsync */
303 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2;
308 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
311 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
313 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
314 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
315 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
316 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
321 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
322 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
323 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
324 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
326 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
327 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
329 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
330 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
338 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
339 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
342 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
343 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
344 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
345 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
346 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
347 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
348 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
349 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
350 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
352 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8;
353 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
354 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
355 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
356 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
357 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
364 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
365 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
367 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
372 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
376 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
383 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
384 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
386 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
391 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
392 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
393 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
394 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
395 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
396 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
397 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
398 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
399 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
401 regp->Attribute[0] = 0x00; /* standard colormap translation */
402 regp->Attribute[1] = 0x01;
403 regp->Attribute[2] = 0x02;
404 regp->Attribute[3] = 0x03;
405 regp->Attribute[4] = 0x04;
406 regp->Attribute[5] = 0x05;
407 regp->Attribute[6] = 0x06;
408 regp->Attribute[7] = 0x07;
409 regp->Attribute[8] = 0x08;
410 regp->Attribute[9] = 0x09;
411 regp->Attribute[10] = 0x0A;
412 regp->Attribute[11] = 0x0B;
413 regp->Attribute[12] = 0x0C;
414 regp->Attribute[13] = 0x0D;
415 regp->Attribute[14] = 0x0E;
416 regp->Attribute[15] = 0x0F;
417 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
419 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
420 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
421 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
422 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
439 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
466 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
468 regp->crtc_eng_ctrl = 0;
471 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
474 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
478 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
480 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
483 regp->CRTC[NV_CIO_CRE_53] = 0;
484 regp->CRTC[NV_CIO_CRE_54] = 0;
488 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
490 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
492 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
496 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
506 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
510 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
512 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
516 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
519 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
521 regp->crtc_830 = mode->crtc_vdisplay - 3;
522 regp->crtc_834 = mode->crtc_vdisplay - 1;
526 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
529 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
531 regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
535 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
536 regp->CRTC[NV_CIO_CRE_86] = 0x1;
539 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8;
542 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
548 regp->nv10_cursync = (1 << 25);
550 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
554 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
556 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
558 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
559 regp->tv_setup = 0;
564 regp->ramdac_8c0 = 0x100;
565 regp->ramdac_a20 = 0x0;
566 regp->ramdac_a24 = 0xfffff;
567 regp->ramdac_a34 = 0x1;
750 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
773 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
774 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8;
775 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
777 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
778 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
780 regp->ramdac_gen_ctrl);
782 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
783 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
785 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
786 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
789 regp->fb_start = nv_crtc->fb.offset & ~3;
790 regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8);
791 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_START, regp->fb_start);
797 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
798 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
799 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
800 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
803 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
804 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);