Lines Matching refs:dev_priv
51 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
52 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
66 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
67 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
105 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 struct nv04_mode_state *state = &dev_priv->mode_reg;
128 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2))
137 if (dev_priv->card_type == NV_40)
140 if (dev_priv->chipset < 0x41)
232 struct drm_nouveau_private *dev_priv = dev->dev_private;
234 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
437 struct drm_nouveau_private *dev_priv = dev->dev_private;
439 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
440 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
477 if (dev_priv->chipset >= 0x11)
510 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
518 if (dev_priv->card_type >= NV_30)
524 if (dev_priv->card_type == NV_40)
528 if (dev_priv->card_type >= NV_30)
534 if (dev_priv->card_type == NV_40) {
546 if (dev_priv->card_type >= NV_10)
555 if (dev_priv->chipset >= 0x11)
585 struct drm_nouveau_private *dev_priv = dev->dev_private;
595 if (dev_priv->card_type == NV_40)
596 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
605 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
606 struct nv04_mode_state *state = &dev_priv->mode_reg;
608 struct nv04_mode_state *saved = &dev_priv->saved_reg;
626 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
628 uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
633 nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg);
642 struct drm_nouveau_private *dev_priv = dev->dev_private;
655 if (dev_priv->card_type == NV_40) {
665 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
668 nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg);
703 struct drm_nouveau_private *dev_priv = dev->dev_private;
707 rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC;
714 nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg);
749 struct drm_nouveau_private *dev_priv = dev->dev_private;
750 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
802 if (dev_priv->card_type >= NV_30) {
855 struct drm_nouveau_private *dev_priv = dev->dev_private;
857 if (dev_priv->chipset == 0x11) {
874 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
875 struct drm_device *dev = dev_priv->dev;
898 if (dev_priv->chipset >= 0x11)