Lines Matching refs:dev_priv
45 struct drm_nouveau_private *dev_priv = dev->dev_private;
46 struct nouveau_engine *engine = &dev_priv->engine;
48 switch (dev_priv->chipset & 0xf0) {
320 if (dev_priv->chipset == 0x50)
411 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
422 struct drm_nouveau_private *dev_priv = dev->dev_private;
424 if (dev_priv->chipset >= 0x40)
439 struct drm_nouveau_private *dev_priv = dev->dev_private;
443 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
450 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
451 0, dev_priv->vram_size,
457 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
463 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
464 dev_priv->gart_info.aper_size,
469 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
477 nouveau_channel_free(dev_priv->channel);
478 dev_priv->channel = NULL;
512 struct drm_nouveau_private *dev_priv = dev->dev_private;
524 engine = &dev_priv->engine;
525 spin_lock_init(&dev_priv->context_switch_lock);
665 struct drm_nouveau_private *dev_priv = dev->dev_private;
666 struct nouveau_engine *engine = &dev_priv->engine;
670 if (dev_priv->channel) {
671 nouveau_channel_free(dev_priv->channel);
672 dev_priv->channel = NULL;
686 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
687 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
768 struct drm_nouveau_private *dev_priv = dev->dev_private;
770 dev_priv->apertures = nouveau_get_apertures(dev);
771 if (!dev_priv->apertures)
778 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
784 struct drm_nouveau_private *dev_priv;
789 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
790 if (!dev_priv) {
794 dev->dev_private = dev_priv;
795 dev_priv->dev = dev;
797 dev_priv->flags = flags & NOUVEAU_FLAGS;
802 dev_priv->wq = create_workqueue("nouveau");
803 if (!dev_priv->wq) {
815 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
816 if (!dev_priv->mmio) {
839 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
843 dev_priv->chipset = 0x05;
845 dev_priv->chipset = 0x04;
847 dev_priv->chipset = 0xff;
849 switch (dev_priv->chipset & 0xf0) {
854 dev_priv->card_type = dev_priv->chipset & 0xf0;
858 dev_priv->card_type = NV_40;
864 dev_priv->card_type = NV_50;
867 dev_priv->card_type = NV_C0;
876 dev_priv->card_type, reg0);
883 if (dev_priv->card_type >= NV_40) {
888 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
889 dev_priv->ramin =
891 dev_priv->ramin_size);
892 if (!dev_priv->ramin) {
898 dev_priv->ramin_size = 1 * 1024 * 1024;
899 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
900 dev_priv->ramin_size);
901 if (!dev_priv->ramin) {
912 dev_priv->flags |= NV_NFORCE;
914 dev_priv->flags |= NV_NFORCE2;
924 iounmap(dev_priv->ramin);
926 iounmap(dev_priv->mmio);
928 destroy_workqueue(dev_priv->wq);
930 kfree(dev_priv);
942 struct drm_nouveau_private *dev_priv = dev->dev_private;
943 struct nouveau_engine *engine = &dev_priv->engine;
950 iounmap(dev_priv->mmio);
951 iounmap(dev_priv->ramin);
953 kfree(dev_priv);
961 struct drm_nouveau_private *dev_priv = dev->dev_private;
966 getparam->value = dev_priv->chipset;
983 getparam->value = dev_priv->fb_phys;
986 getparam->value = dev_priv->gart_info.aper_base;
998 getparam->value = dev_priv->fb_available_size;
1001 getparam->value = dev_priv->gart_info.aper_size;
1004 getparam->value = dev_priv->vm_vram_base;
1007 getparam->value = dev_priv->engine.timer.read(dev);
1013 if (dev_priv->chipset >= 0x40) {
1045 struct drm_nouveau_private *dev_priv = dev->dev_private;
1046 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;