Lines Matching refs:dev_priv
71 struct drm_nouveau_private *dev_priv = dev->dev_private;
77 for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
78 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
79 handle >>= dev_priv->ramht_bits;
82 if (dev_priv->card_type < NV_50)
83 hash ^= channel << (dev_priv->ramht_bits - 4);
94 struct drm_nouveau_private *dev_priv = dev->dev_private;
97 if (dev_priv->card_type < NV_40)
105 struct drm_nouveau_private *dev_priv = dev->dev_private;
106 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
116 if (dev_priv->card_type < NV_40) {
121 if (dev_priv->card_type < NV_50) {
152 if (co >= dev_priv->ramht_size)
163 struct drm_nouveau_private *dev_priv = dev->dev_private;
164 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
191 if (co >= dev_priv->ramht_size)
205 struct drm_nouveau_private *dev_priv = dev->dev_private;
206 struct nouveau_engine *engine = &dev_priv->engine;
214 if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
224 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
236 pramin = &dev_priv->ramin_heap;
278 struct drm_nouveau_private *dev_priv = dev->dev_private;
282 INIT_LIST_HEAD(&dev_priv->gpuobj_list);
290 struct drm_nouveau_private *dev_priv = dev->dev_private;
295 if (dev_priv->card_type < NV_50) {
297 dev_priv->ramht_offset, ~0, dev_priv->ramht_size,
299 &dev_priv->ramht, NULL);
310 struct drm_nouveau_private *dev_priv = dev->dev_private;
314 nouveau_gpuobj_del(dev, &dev_priv->ramht);
320 struct drm_nouveau_private *dev_priv = dev->dev_private;
326 list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) {
339 struct drm_nouveau_private *dev_priv = dev->dev_private;
340 struct nouveau_engine *engine = &dev_priv->engine;
346 if (!dev_priv || !pgpuobj || !(*pgpuobj))
386 struct drm_nouveau_private *dev_priv = dev->dev_private;
390 if (dev_priv->card_type < NV_50) {
433 struct drm_nouveau_private *dev_priv = dev->dev_private;
441 if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
556 struct drm_nouveau_private *dev_priv = dev->dev_private;
571 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
592 dev_priv->engine.instmem.flush(dev);
612 struct drm_nouveau_private *dev_priv = dev->dev_private;
614 if (dev_priv->card_type >= NV_50)
616 if (dev_priv->card_type >= NV_40)
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
655 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
664 offset += dev_priv->gart_info.aper_base;
679 if (dev_priv->card_type < NV_50) {
729 struct drm_nouveau_private *dev_priv = dev->dev_private;
732 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
733 (dev_priv->card_type >= NV_50 &&
734 dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
736 offset + dev_priv->vm_gart_base,
742 if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
743 *gpuobj = dev_priv->gart_info.sg_ctxdma;
752 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
815 struct drm_nouveau_private *dev_priv = dev->dev_private;
830 if (dev_priv->card_type >= NV_50) {
840 if (dev_priv->card_type >= NV_40) {
854 dev_priv->engine.instmem.flush(dev);
865 struct drm_nouveau_private *dev_priv;
870 dev_priv = chan->dev->dev_private;
878 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
887 struct drm_nouveau_private *dev_priv = dev->dev_private;
900 size += dev_priv->engine.graph.grctx_size;
902 if (dev_priv->card_type == NV_50) {
936 struct drm_nouveau_private *dev_priv = dev->dev_private;
937 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
957 if (dev_priv->card_type >= NV_50) {
960 vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
972 pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 2;
974 dev_priv->gart_info.sg_ctxdma,
982 pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 2;
983 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
985 dev_priv->vm_vram_pt[i],
999 if (dev_priv->card_type < NV_50) {
1000 ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht,
1014 if (dev_priv->card_type >= NV_50) {
1016 0, dev_priv->vm_end,
1025 0, dev_priv->fb_available_size,
1041 if (dev_priv->card_type >= NV_50) {
1044 if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
1046 dev_priv->gart_info.aper_size,
1049 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
1070 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
1091 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
1104 struct drm_nouveau_private *dev_priv = dev->dev_private;
1108 if (dev_priv->card_type < NV_50) {
1109 dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram);
1110 if (!dev_priv->susres.ramin_copy)
1113 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
1114 dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i);
1118 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1138 struct drm_nouveau_private *dev_priv = dev->dev_private;
1141 if (dev_priv->card_type < NV_50) {
1142 vfree(dev_priv->susres.ramin_copy);
1143 dev_priv->susres.ramin_copy = NULL;
1147 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1159 struct drm_nouveau_private *dev_priv = dev->dev_private;
1163 if (dev_priv->card_type < NV_50) {
1164 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
1165 nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]);
1170 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
1176 dev_priv->engine.instmem.flush(dev);
1185 struct drm_nouveau_private *dev_priv = dev->dev_private;
1187 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;