Lines Matching refs:status
139 uint32_t status, reassign;
143 while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
154 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
200 status &= ~NV_PFIFO_INTR_CACHE_ERROR;
203 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
206 status &= ~NV_PFIFO_INTR_DMA_PUSHER;
216 if (status & NV_PFIFO_INTR_SEMAPHORE) {
219 status &= ~NV_PFIFO_INTR_SEMAPHORE;
230 if (status) {
232 status, chid);
233 nv_wr32(dev, NV03_PFIFO_INTR_0, status);
234 status = 0;
240 if (status) {
570 uint32_t status;
572 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
575 if (status & NV_PGRAPH_INTR_NOTIFY) {
578 status &= ~NV_PGRAPH_INTR_NOTIFY;
582 if (status & NV_PGRAPH_INTR_ERROR) {
585 status &= ~NV_PGRAPH_INTR_ERROR;
589 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
590 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
597 if (status) {
598 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
599 nv_wr32(dev, NV03_PGRAPH_INTR, status);
632 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
657 uint32_t addr, mp10, status, pc, oplow, ophigh;
668 status = nv_rd32(dev, addr + 0x14);
669 if (!status)
678 nouveau_print_enum_names(status,
799 uint32_t status = nv_rd32(dev, 0x400108);
804 if (!status && display) {
813 if (status & 0x001) {
871 status &= ~0x001;
875 if (status && display) {
882 if (status & 0x002) {
911 status &= ~0x002;
915 if (status & 0x004) {
933 status &= ~0x004;
937 if (status & 0x008) {
958 status &= ~0x008;
962 if (status & 0x010) {
983 status &= ~0x010;
986 /* Unknown, not seen yet... 0x402000 is the only trap status reg
989 if (status & 0x20) {
995 /* no status modifiction on purpose */
999 if (status & 0x040) {
1003 status &= ~0x040;
1007 if (status & 0x080) {
1011 status &= ~0x080;
1016 if (status & 0x100) {
1020 status &= ~0x100;
1023 if (status) {
1026 status);
1027 nv_wr32(dev, 0x400108, status);
1047 uint32_t status;
1049 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1051 if (status & 0x00000001) {
1056 status &= ~0x00000001;
1062 if (status & 0x00000002) {
1067 status &= ~0x00000002;
1074 if (status & 0x00000010) {
1081 status &= ~0x00000010;
1086 if (status & 0x00000020) {
1091 status &= ~0x00000020;
1096 if (status & 0x00000040) {
1101 status &= ~0x00000040;
1106 if (status & 0x00001000) {
1117 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1121 if (status & 0x00010000) {
1126 status &= ~0x00010000;
1132 if (status & 0x00100000) {
1142 status &= ~0x00100000;
1149 if (status & 0x00200000) {
1151 status &= ~0x00200000;
1159 if (status & 0x01000000) {
1164 status &= ~0x01000000;
1173 if (status) {
1175 status);
1176 nv_wr32(dev, NV03_PGRAPH_INTR, status);
1208 uint32_t status;
1211 status = nv_rd32(dev, NV03_PMC_INTR_0);
1212 if (!status)
1217 if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
1219 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
1222 if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
1228 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
1231 if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
1232 nouveau_crtc_irq_handler(dev, (status>>24)&3);
1233 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
1236 if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1239 status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1243 if (status)
1244 NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);