Lines Matching refs:pll1
224 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
231 /* model specific additions to generic pll1 and pll2 set up above */
233 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
248 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
250 if (oldpll1 == pll1 && oldpll2 == pll2)
284 NVWriteRAMDAC(dev, 0, reg1, pll1);
394 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
402 pllvals->log2P = (pll1 >> 16) & 0x7;
408 if (!(pll1 & 0x1100))
411 pllvals->NM1 = pll1 & 0xffff;
416 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
417 pllvals->M2 = (pll1 >> 4) & 0x7;
418 pllvals->N2 = ((pll1 >> 21) & 0x18) |
419 ((pll1 >> 19) & 0x7);
438 uint32_t reg1, pll1, pll2 = 0;
447 pll1 = nvReadMC(dev, reg1);
469 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);