Lines Matching defs:regp
658 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
662 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
664 nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, ®p->pllvals);
669 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
671 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
674 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
676 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
678 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
679 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
680 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
681 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
682 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
683 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
684 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
685 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
689 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
690 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
694 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
696 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
697 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
701 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
702 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
706 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
709 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
710 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
712 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
715 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
718 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
719 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
720 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
723 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
733 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
738 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
740 nouveau_hw_setpll(dev, pllreg, ®p->pllvals);
745 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
747 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
750 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
752 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
754 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
755 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
756 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
757 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
758 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
759 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
760 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
761 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
766 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
767 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
771 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
773 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
774 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
778 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
779 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
780 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
781 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
783 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
786 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
789 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
790 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
791 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
795 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
803 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
806 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
809 rd_cio_state(dev, head, regp, i);
813 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
817 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
820 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
827 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
830 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
833 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
837 wr_cio_state(dev, head, regp, i);
841 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
845 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
854 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
857 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
858 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
859 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
860 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
861 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
862 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
863 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
865 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
866 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
867 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
870 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
871 rd_cio_state(dev, head, regp, 0x9f);
874 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
875 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
876 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
877 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
878 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
881 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
882 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
885 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
888 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
891 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
892 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
895 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
897 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
898 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
900 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
901 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
902 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
903 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
907 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
908 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
911 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
912 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
913 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
915 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
916 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
919 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
927 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
937 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
949 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
950 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
951 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
954 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
957 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
960 if (regp->crtc_cfg == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
967 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
969 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
970 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
971 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
972 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
973 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
974 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
975 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
976 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
977 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
980 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
981 wr_cio_state(dev, head, regp, 0x9f);
984 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
985 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
986 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
987 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
990 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
992 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
993 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
995 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
996 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
997 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
998 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
1009 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
1010 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
1013 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
1014 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
1015 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
1017 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
1018 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
1021 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);