Lines Matching defs:pv
160 setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv)
166 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
180 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
182 NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
185 NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
216 struct nouveau_pll_vals *pv)
224 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
225 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
227 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
233 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
234 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
294 struct nouveau_pll_vals *pv)
307 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
309 0xc << 28 | pv->log2P << 16;
313 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
330 Pval2 = pv->log2P + pll_lim.log2p_bias;
374 struct nouveau_pll_vals *pv)
382 setPLL_double_highregs(dev, reg1, pv);
384 setPLL_double_lowregs(dev, reg1, pv);
386 setPLL_single(dev, reg1, pv);
481 nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
484 if (!pv->M1 || !pv->M2)
487 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
526 struct nouveau_pll_vals pv;
531 nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &pv);
533 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
534 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
535 pv.log2P <= pll_lim.max_log2p)
541 pv.M1 = pll_lim.vco1.max_m;
542 pv.N1 = pll_lim.vco1.min_n;
543 pv.log2P = pll_lim.max_usable_log2p;
544 nouveau_hw_setpll(dev, pllreg, &pv);