Lines Matching refs:wm
2734 * @wm: chip FIFO params
2750 struct intel_watermark_params *wm,
2764 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2768 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2773 if (wm_size > (long)wm->max_wm)
2774 wm_size = wm->max_wm;
2776 wm_size = wm->default_wm;
2948 unsigned long wm;
2963 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2967 reg |= wm << DSPFW_SR_SHIFT;
2972 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2976 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2980 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2984 reg |= wm & DSPFW_HPLL_SR_MASK;
2988 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2992 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;