Lines Matching refs:dpll
3504 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3767 dpll = DPLL_VGA_MODE_DIS;
3771 dpll |= DPLLB_MODE_LVDS;
3773 dpll |= DPLLB_MODE_DAC_SERIAL;
3775 dpll |= DPLL_DVO_HIGH_SPEED;
3778 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3780 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3783 dpll |= DPLL_DVO_HIGH_SPEED;
3787 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3789 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3792 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3794 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3804 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3807 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3811 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3814 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3817 dpll |= PLL_P1_DIVIDE_BY_TWO;
3819 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3821 dpll |= PLL_P2_DIVIDE_BY_4;
3826 dpll |= PLL_REF_INPUT_TVCLKINBC;
3828 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3829 dpll |= 3;
3831 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3833 dpll |= PLL_REF_INPUT_DREFCLK;
3860 dpll |= DPLL_VCO_ENABLE;
3878 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3973 I915_WRITE(dpll_reg, dpll);
3987 I915_WRITE(dpll_reg, dpll);
4519 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4523 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4539 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4545 switch (dpll & DPLL_MODE_MASK) {
4547 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4551 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4556 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4569 if ((dpll & PLL_REF_INPUT_MASK) ==
4575 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4578 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4581 if (dpll & PLL_P2_DIVIDE_BY_4)
4664 int dpll = I915_READ(dpll_reg);
4672 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4679 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4680 I915_WRITE(dpll_reg, dpll);
4681 dpll = I915_READ(dpll_reg);
4683 dpll = I915_READ(dpll_reg);
4684 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4704 int dpll = I915_READ(dpll_reg);
4723 dpll |= DISPLAY_RATE_SELECT_FPA1;
4724 I915_WRITE(dpll_reg, dpll);
4725 dpll = I915_READ(dpll_reg);
4727 dpll = I915_READ(dpll_reg);
4728 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5913 /* 855 & before need to leave pipe A & dpll A up */