Lines Matching refs:dev_priv
638 struct drm_i915_private *dev_priv = dev->dev_private;
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
671 struct drm_i915_private *dev_priv = dev->dev_private;
802 struct drm_i915_private *dev_priv = dev->dev_private;
864 struct drm_i915_private *dev_priv = dev->dev_private;
987 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1069 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071 if (fb->pitch < dev_priv->cfb_pitch)
1072 dev_priv->cfb_pitch = fb->pitch;
1075 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1076 dev_priv->cfb_fence = obj_priv->fence_reg;
1077 dev_priv->cfb_plane = intel_crtc->plane;
1078 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1095 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1098 fbc_ctl |= dev_priv->cfb_fence;
1102 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1150 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1151 dev_priv->cfb_fence = obj_priv->fence_reg;
1152 dev_priv->cfb_plane = intel_crtc->plane;
1156 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1207 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1208 dev_priv->cfb_fence = obj_priv->fence_reg;
1209 dev_priv->cfb_plane = intel_crtc->plane;
1215 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1258 if (!dev_priv->display.fbc_enabled)
1261 return dev_priv->display.fbc_enabled(dev);
1266 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1268 if (!dev_priv->display.enable_fbc)
1271 dev_priv->display.enable_fbc(crtc, interval);
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1278 if (!dev_priv->display.disable_fbc)
1281 dev_priv->display.disable_fbc(dev);
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1347 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1350 if (intel_fb->obj->size > dev_priv->cfb_size) {
1353 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1360 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1366 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1371 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1376 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1386 if ((fb->pitch > dev_priv->cfb_pitch) ||
1387 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1388 (plane != dev_priv->cfb_plane))
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1937 if (dev_priv->pch_pf_size &&
1947 dev_priv->pch_pf_pos);
1949 dev_priv->pch_pf_size);
2098 if (dev_priv->cfb_plane == plane &&
2099 dev_priv->display.disable_fbc)
2100 dev_priv->display.disable_fbc(dev);
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2318 if (dev_priv->cfb_plane == plane &&
2319 dev_priv->display.disable_fbc)
2320 dev_priv->display.disable_fbc(dev);
2333 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) {
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2390 dev_priv->display.dpms(crtc, mode);
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2951 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2952 dev_priv->fsb_freq, dev_priv->mem_freq);
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3178 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3179 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3248 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3443 if (!dev_priv->display.update_wm)
3473 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3566 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3567 refclk = dev_priv->lvds_ssc_freq * 1000;
3595 if (is_lvds && dev_priv->lvds_downclock_avail) {
3597 dev_priv->lvds_downclock,
3662 switch (dev_priv->edp_bpp/3) {
3735 if (dev_priv->lvds_use_ssc) {
3830 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3852 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3924 lvds |= dev_priv->lvds_border_bits;
3939 if (dev_priv->lvds_dither) {
4099 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4276 if (!dev_priv->info->cursor_needs_physical) {
4307 if (dev_priv->info->cursor_needs_physical) {
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4633 drm_i915_private_t *dev_priv = dev->dev_private;
4637 dev_priv->busy = false;
4639 queue_work(dev_priv->wq, &dev_priv->idle_work);
4648 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4654 queue_work(dev_priv->wq, &dev_priv->idle_work);
4660 drm_i915_private_t *dev_priv = dev->dev_private;
4669 if (!dev_priv->lvds_downclock_avail)
4700 drm_i915_private_t *dev_priv = dev->dev_private;
4709 if (!dev_priv->lvds_downclock_avail)
4746 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4748 struct drm_device *dev = dev_priv->dev;
4758 i915_update_gfx_val(dev_priv);
4791 drm_i915_private_t *dev_priv = dev->dev_private;
4799 if (!dev_priv->busy) {
4808 dev_priv->busy = true;
4810 mod_timer(&dev_priv->idle_timer, jiffies +
4865 drm_i915_private_t *dev_priv = dev->dev_private;
4905 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4913 drm_i915_private_t *dev_priv = dev->dev_private;
4914 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4921 drm_i915_private_t *dev_priv = dev->dev_private;
4922 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4929 drm_i915_private_t *dev_priv = dev->dev_private;
4931 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4949 struct drm_i915_private *dev_priv = dev->dev_private;
5117 drm_i915_private_t *dev_priv = dev->dev_private;
5144 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5145 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5146 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5147 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5162 drm_i915_private_t *dev_priv = dev->dev_private;
5167 if (!dev_priv) {
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5475 dev_priv->fmax = fstart; /* IPS callback will increase this */
5476 dev_priv->fstart = fstart;
5478 dev_priv->max_delay = fmax;
5479 dev_priv->min_delay = fmin;
5480 dev_priv->cur_delay = fstart;
5503 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5505 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5506 dev_priv->last_count2 = I915_READ(0x112f4);
5507 getrawmonotonic(&dev_priv->last_time2);
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5523 ironlake_set_drps(dev, dev_priv->fstart);
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5614 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5733 if (dev_priv->renderctx == NULL)
5734 dev_priv->renderctx = intel_alloc_context_page(dev);
5735 if (dev_priv->renderctx) {
5737 obj_priv = to_intel_bo(dev_priv->renderctx);
5758 if (dev_priv->pwrctx) {
5759 obj_priv = to_intel_bo(dev_priv->pwrctx);
5765 dev_priv->pwrctx = pwrctx;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5785 dev_priv->display.dpms = ironlake_crtc_dpms;
5787 dev_priv->display.dpms = i9xx_crtc_dpms;
5791 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5792 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5793 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5795 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5796 dev_priv->display.enable_fbc = g4x_enable_fbc;
5797 dev_priv->display.disable_fbc = g4x_disable_fbc;
5799 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5800 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5801 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5808 dev_priv->display.get_display_clock_speed =
5811 dev_priv->display.get_display_clock_speed =
5814 dev_priv->display.get_display_clock_speed =
5817 dev_priv->display.get_display_clock_speed =
5820 dev_priv->display.get_display_clock_speed =
5823 dev_priv->display.get_display_clock_speed =
5826 dev_priv->display.get_display_clock_speed =
5833 dev_priv->display.update_wm = ironlake_update_wm;
5837 dev_priv->display.update_wm = NULL;
5840 dev_priv->display.update_wm = NULL;
5843 dev_priv->is_ddr3,
5844 dev_priv->fsb_freq,
5845 dev_priv->mem_freq)) {
5849 (dev_priv->is_ddr3 == 1) ? "3": "2",
5850 dev_priv->fsb_freq, dev_priv->mem_freq);
5853 dev_priv->display.update_wm = NULL;
5855 dev_priv->display.update_wm = pineview_update_wm;
5857 dev_priv->display.update_wm = g4x_update_wm;
5859 dev_priv->display.update_wm = i965_update_wm;
5861 dev_priv->display.update_wm = i9xx_update_wm;
5862 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5864 dev_priv->display.update_wm = i9xx_update_wm;
5865 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5867 dev_priv->display.update_wm = i830_update_wm;
5869 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5871 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5884 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5992 dev_priv->num_pipe = 2;
5994 dev_priv->num_pipe = 1;
5996 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5998 for (i = 0; i < dev_priv->num_pipe; i++) {
6014 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6015 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6042 del_timer_sync(&dev_priv->idle_timer);
6044 if (dev_priv->display.disable_fbc)
6045 dev_priv->display.disable_fbc(dev);
6047 if (dev_priv->renderctx) {
6050 obj_priv = to_intel_bo(dev_priv->renderctx);
6053 i915_gem_object_unpin(dev_priv->renderctx);
6054 drm_gem_object_unreference(dev_priv->renderctx);
6057 if (dev_priv->pwrctx) {
6060 obj_priv = to_intel_bo(dev_priv->pwrctx);
6063 i915_gem_object_unpin(dev_priv->pwrctx);
6064 drm_gem_object_unreference(dev_priv->pwrctx);
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6109 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6114 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);