Lines Matching refs:p1
53 int p1, p2;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
727 clock->p = clock->p1 * clock->p2;
739 clock->p = clock->p1 * clock->p2;
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
837 for (clock.p1 = limit->p1.min;
838 clock.p1 <= limit->p1.max; clock.p1++) {
900 for (clock.p1 = limit->p1.max;
901 clock.p1 >= limit->p1.min; clock.p1--) {
934 clock.p1 = 2;
940 clock.p1 = 1;
957 clock.p1 = 2;
963 clock.p1 = 1;
970 clock.p = (clock.p1 * clock.p2);
3582 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3617 clock.p1 = 2;
3624 clock.p1 = 1;
3785 /* compute bitmask from p1 value */
3787 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3789 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3792 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3794 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3814 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3816 if (clock.p1 == 2)
3819 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4539 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4576 clock.p1 = 2;
4578 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>