Lines Matching refs:dev_priv
34 struct drm_i915_private *dev_priv = dev->dev_private;
48 struct drm_i915_private *dev_priv = dev->dev_private;
60 array = dev_priv->save_palette_a;
62 array = dev_priv->save_palette_b;
70 struct drm_i915_private *dev_priv = dev->dev_private;
82 array = dev_priv->save_palette_a;
84 array = dev_priv->save_palette_b;
92 struct drm_i915_private *dev_priv = dev->dev_private;
100 struct drm_i915_private *dev_priv = dev->dev_private;
109 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct drm_i915_private *dev_priv = dev->dev_private;
126 struct drm_i915_private *dev_priv = dev->dev_private;
131 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
134 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
135 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
150 dev_priv->saveCR[i] =
153 dev_priv->saveCR[0x11] &= ~0x80;
157 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
159 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
161 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
166 dev_priv->saveGR[i] =
169 dev_priv->saveGR[0x10] =
171 dev_priv->saveGR[0x11] =
173 dev_priv->saveGR[0x18] =
178 dev_priv->saveSR[i] =
184 struct drm_i915_private *dev_priv = dev->dev_private;
189 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
190 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
203 dev_priv->saveSR[i]);
207 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
209 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
214 dev_priv->saveGR[i]);
217 dev_priv->saveGR[0x10]);
219 dev_priv->saveGR[0x11]);
221 dev_priv->saveGR[0x18]);
226 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
228 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
232 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
237 struct drm_i915_private *dev_priv = dev->dev_private;
243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
255 dev_priv->saveFPA0 = I915_READ(FPA0);
256 dev_priv->saveFPA1 = I915_READ(FPA1);
257 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
263 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
274 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
276 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
277 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
279 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
280 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
281 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
283 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
284 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
285 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
286 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
287 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
288 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
289 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
292 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
293 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
294 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
295 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
296 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
298 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
299 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
302 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
312 dev_priv->saveFPB0 = I915_READ(FPB0);
313 dev_priv->saveFPB1 = I915_READ(FPB1);
314 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
320 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
331 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
333 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
334 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
336 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
337 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
338 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
340 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
341 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
342 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
343 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
344 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
345 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
346 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
349 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
350 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
351 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
352 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
353 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
355 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
356 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
359 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
365 struct drm_i915_private *dev_priv = dev->dev_private;
389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
401 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
402 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
415 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
416 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
417 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
418 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
419 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
421 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
424 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
425 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
426 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
427 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
429 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
430 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
432 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
433 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
434 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
436 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
437 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
438 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
439 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
440 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
441 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
442 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
446 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
447 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
448 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
449 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
450 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
452 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
453 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
456 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
460 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
464 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
465 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
470 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
471 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
473 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
477 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
483 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
484 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
485 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
486 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
487 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
488 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
490 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
493 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
494 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
495 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
496 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
498 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
499 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
501 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
502 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
503 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
505 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
506 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
507 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
508 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
509 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
510 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
511 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
515 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
516 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
517 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
518 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
519 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
521 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
522 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
525 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
529 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
537 struct drm_i915_private *dev_priv = dev->dev_private;
540 dev_priv->saveDSPARB = I915_READ(DSPARB);
547 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
548 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
549 dev_priv->saveCURABASE = I915_READ(CURABASE);
550 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
551 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
552 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
554 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
558 dev_priv->saveADPA = I915_READ(PCH_ADPA);
560 dev_priv->saveADPA = I915_READ(ADPA);
565 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
566 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
567 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
568 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
569 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
570 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
572 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
573 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
574 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
575 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
577 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
579 dev_priv->saveLVDS = I915_READ(LVDS);
583 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
586 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
587 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
588 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
590 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
591 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
592 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
597 dev_priv->saveDP_B = I915_READ(DP_B);
598 dev_priv->saveDP_C = I915_READ(DP_C);
599 dev_priv->saveDP_D = I915_READ(DP_D);
600 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
601 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
602 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
603 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
604 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
605 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
606 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
607 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
613 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
615 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
617 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
618 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
619 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
620 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
625 dev_priv->saveVGA0 = I915_READ(VGA0);
626 dev_priv->saveVGA1 = I915_READ(VGA1);
627 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
629 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
631 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
638 struct drm_i915_private *dev_priv = dev->dev_private;
641 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
645 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
646 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
647 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
648 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
649 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
650 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
651 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
652 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
660 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
661 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
662 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
663 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
664 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
665 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
667 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
671 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
673 I915_WRITE(ADPA, dev_priv->saveADPA);
677 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
680 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
682 I915_WRITE(LVDS, dev_priv->saveLVDS);
685 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
688 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
689 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
690 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
691 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
692 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
693 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
694 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
695 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
697 dev_priv->saveMCHBAR_RENDER_STANDBY);
699 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
700 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
701 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
702 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
703 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
704 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
705 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
710 I915_WRITE(DP_B, dev_priv->saveDP_B);
711 I915_WRITE(DP_C, dev_priv->saveDP_C);
712 I915_WRITE(DP_D, dev_priv->saveDP_D);
719 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
722 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
725 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
726 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
727 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
728 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
733 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
735 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
736 I915_WRITE(VGA0, dev_priv->saveVGA0);
737 I915_WRITE(VGA1, dev_priv->saveVGA1);
738 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
747 struct drm_i915_private *dev_priv = dev->dev_private;
750 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
753 dev_priv->saveHWS = I915_READ(HWS_PGA);
759 dev_priv->saveDEIER = I915_READ(DEIER);
760 dev_priv->saveDEIMR = I915_READ(DEIMR);
761 dev_priv->saveGTIER = I915_READ(GTIER);
762 dev_priv->saveGTIMR = I915_READ(GTIMR);
763 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
764 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
765 dev_priv->saveMCHBAR_RENDER_STANDBY =
768 dev_priv->saveIER = I915_READ(IER);
769 dev_priv->saveIMR = I915_READ(IMR);
776 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
779 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
783 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
784 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
787 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
793 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
798 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
803 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
806 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
816 struct drm_i915_private *dev_priv = dev->dev_private;
819 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
822 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
828 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
833 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
839 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
841 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
849 I915_WRITE(DEIER, dev_priv->saveDEIER);
850 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
851 I915_WRITE(GTIER, dev_priv->saveGTIER);
852 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
853 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
854 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
856 I915_WRITE (IER, dev_priv->saveIER);
857 I915_WRITE (IMR, dev_priv->saveIMR);
869 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
872 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
875 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
876 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
879 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);