Lines Matching refs:dev_priv
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
144 dev_priv->pipestat[pipe] |= mask;
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
173 i915_enable_pipestat(dev_priv, 1,
176 i915_enable_pipestat(dev_priv, 0,
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
259 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
261 struct drm_device *dev = dev_priv->dev;
279 drm_i915_private_t *dev_priv = dev->dev_private;
281 u8 new_delay = dev_priv->cur_delay;
291 if (dev_priv->cur_delay != dev_priv->max_delay)
292 new_delay = dev_priv->cur_delay - 1;
293 if (new_delay < dev_priv->max_delay)
294 new_delay = dev_priv->max_delay;
296 if (dev_priv->cur_delay != dev_priv->min_delay)
297 new_delay = dev_priv->cur_delay + 1;
298 if (new_delay > dev_priv->min_delay)
299 new_delay = dev_priv->min_delay;
303 dev_priv->cur_delay = new_delay;
310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
315 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
340 READ_BREADCRUMB(dev_priv);
347 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
348 dev_priv->hangcheck_count = 0;
349 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
352 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
376 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
404 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
406 struct drm_device *dev = dev_priv->dev;
414 if (atomic_read(&dev_priv->mm.wedged)) {
419 atomic_set(&dev_priv->mm.wedged, 0);
432 drm_i915_private_t *dev_priv = dev->dev_private;
462 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
530 struct drm_i915_private *dev_priv = dev->dev_private;
539 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
541 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
548 ring = (u32 *)(dev_priv->render_ring.virtual_start
549 + dev_priv->render_ring.size);
550 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
571 struct drm_i915_private *dev_priv = dev->dev_private;
579 spin_lock_irqsave(&dev_priv->error_lock, flags);
580 error = dev_priv->first_error;
581 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
591 error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
620 &dev_priv->render_ring.active_list, list) {
638 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
656 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
685 dev_priv->render_ring.gem_object);
698 &dev_priv->render_ring.active_list, list) {
727 spin_lock_irqsave(&dev_priv->error_lock, flags);
728 if (dev_priv->first_error == NULL) {
729 dev_priv->first_error = error;
732 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
740 struct drm_i915_private *dev_priv = dev->dev_private;
743 spin_lock(&dev_priv->error_lock);
744 error = dev_priv->first_error;
745 dev_priv->first_error = NULL;
746 spin_unlock(&dev_priv->error_lock);
754 struct drm_i915_private *dev_priv = dev->dev_private;
877 struct drm_i915_private *dev_priv = dev->dev_private;
883 atomic_set(&dev_priv->mm.wedged, 1);
888 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
891 queue_work(dev_priv->wq, &dev_priv->error_work);
896 drm_i915_private_t *dev_priv = dev->dev_private;
897 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
940 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
949 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
951 atomic_inc(&dev_priv->irq_received);
971 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
994 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1008 if (hotplug_status & dev_priv->hotplug_supported_mask)
1009 queue_work(dev_priv->wq,
1010 &dev_priv->hotplug_work);
1023 READ_BREADCRUMB(dev_priv);
1031 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1032 dev_priv->hangcheck_count = 0;
1033 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1037 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1041 if (dev_priv->flip_pending_is_done)
1047 if (dev_priv->flip_pending_is_done)
1054 if (!dev_priv->flip_pending_is_done) {
1063 if (!dev_priv->flip_pending_is_done) {
1097 drm_i915_private_t *dev_priv = dev->dev_private;
1104 dev_priv->counter++;
1105 if (dev_priv->counter > 0x7FFFFFFFUL)
1106 dev_priv->counter = 1;
1108 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1113 OUT_RING(dev_priv->counter);
1117 return dev_priv->counter;
1122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1123 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1125 if (dev_priv->trace_irq_seqno == 0)
1128 dev_priv->trace_irq_seqno = seqno;
1133 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1136 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1139 READ_BREADCRUMB(dev_priv));
1141 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1143 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1151 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1152 READ_BREADCRUMB(dev_priv) >= irq_nr);
1157 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1168 drm_i915_private_t *dev_priv = dev->dev_private;
1172 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1196 drm_i915_private_t *dev_priv = dev->dev_private;
1199 if (!dev_priv) {
1212 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1221 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1223 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1226 i915_enable_pipestat(dev_priv, pipe,
1229 i915_enable_pipestat(dev_priv, pipe,
1231 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1240 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1243 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1245 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1248 i915_disable_pipestat(dev_priv, pipe,
1251 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1260 dev_priv->irq_enabled = 1;
1269 drm_i915_private_t *dev_priv = dev->dev_private;
1271 if (!dev_priv) {
1282 drm_i915_private_t *dev_priv = dev->dev_private;
1285 if (!dev_priv) {
1321 drm_i915_private_t *dev_priv = dev->dev_private;
1322 return list_entry(dev_priv->render_ring.request_list.prev,
1335 drm_i915_private_t *dev_priv = dev->dev_private;
1353 if (list_empty(&dev_priv->render_ring.request_list) ||
1355 &dev_priv->render_ring),
1359 dev_priv->hangcheck_count = 0;
1362 if (dev_priv->render_ring.waiting_gem_seqno &&
1363 waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1364 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1368 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1369 waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1370 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1379 if (dev_priv->last_acthd == acthd &&
1380 dev_priv->last_instdone == instdone &&
1381 dev_priv->last_instdone1 == instdone1) {
1382 if (dev_priv->hangcheck_count++ > 1) {
1388 dev_priv->hangcheck_count = 0;
1390 dev_priv->last_acthd = acthd;
1391 dev_priv->last_instdone = instdone;
1392 dev_priv->last_instdone1 = instdone1;
1396 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1403 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1432 dev_priv->irq_mask_reg = ~display_mask;
1433 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1437 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1438 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1445 dev_priv->gt_irq_mask_reg = ~render_mask;
1446 dev_priv->gt_irq_enable_reg = render_mask;
1449 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1452 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1463 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1464 dev_priv->pch_irq_enable_reg = hotplug_mask;
1467 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1468 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1475 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1485 atomic_set(&dev_priv->irq_received, 0);
1487 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1488 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1514 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1518 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1521 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1523 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1529 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1531 dev_priv->pipestat[0] = 0;
1532 dev_priv->pipestat[1] = 0;
1538 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1556 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1564 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1566 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1568 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1570 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1572 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1574 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1614 if (!dev_priv)
1617 dev_priv->vblank_pipe = 0;