Lines Matching refs:dev_priv
789 * reaches 0, dev_priv->pending_flip_queue will be woken up.
866 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
867 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
868 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
869 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
896 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
897 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
898 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
900 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
904 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
907 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1102 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1103 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1104 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1105 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1106 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1107 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1108 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1109 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1153 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1154 (dev_priv->render_ring.status_page.page_addr))[reg])
1155 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)