Lines Matching refs:dev_priv
73 drm_i915_private_t *dev_priv = dev->dev_private;
80 lock = &dev_priv->mm.active_list_lock;
81 head = &dev_priv->render_ring.active_list;
85 head = &dev_priv->mm.inactive_list;
89 head = &dev_priv->mm.flushing_list;
177 drm_i915_private_t *dev_priv = dev->dev_private;
181 list_for_each_entry(gem_request, &dev_priv->render_ring.request_list,
194 drm_i915_private_t *dev_priv = dev->dev_private;
196 if (dev_priv->render_ring.status_page.page_addr != NULL) {
198 i915_get_gem_seqno(dev, &dev_priv->render_ring));
203 dev_priv->mm.waiting_gem_seqno);
204 seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
213 drm_i915_private_t *dev_priv = dev->dev_private;
247 atomic_read(&dev_priv->irq_received));
248 if (dev_priv->render_ring.status_page.page_addr != NULL) {
250 i915_get_gem_seqno(dev, &dev_priv->render_ring));
255 dev_priv->mm.waiting_gem_seqno);
257 dev_priv->mm.irq_gem_seqno);
265 drm_i915_private_t *dev_priv = dev->dev_private;
268 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
269 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
270 for (i = 0; i < dev_priv->num_fence_regs; i++) {
271 struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
300 drm_i915_private_t *dev_priv = dev->dev_private;
304 hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr;
333 drm_i915_private_t *dev_priv = dev->dev_private;
338 spin_lock(&dev_priv->mm.active_list_lock);
340 list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list,
347 spin_unlock(&dev_priv->mm.active_list_lock);
358 spin_unlock(&dev_priv->mm.active_list_lock);
367 drm_i915_private_t *dev_priv = dev->dev_private;
371 if (!dev_priv->render_ring.gem_object) {
376 virt = dev_priv->render_ring.virtual_start;
378 for (off = 0; off < dev_priv->render_ring.size; off += 4) {
390 drm_i915_private_t *dev_priv = dev->dev_private;
398 seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size);
438 drm_i915_private_t *dev_priv = dev->dev_private;
443 spin_lock_irqsave(&dev_priv->error_lock, flags);
444 if (!dev_priv->first_error) {
449 error = dev_priv->first_error;
523 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
532 drm_i915_private_t *dev_priv = dev->dev_private;
544 drm_i915_private_t *dev_priv = dev->dev_private;
562 drm_i915_private_t *dev_priv = dev->dev_private;
584 drm_i915_private_t *dev_priv = dev->dev_private;
600 drm_i915_private_t *dev_priv = dev->dev_private;
633 drm_i915_private_t *dev_priv = dev->dev_private;
644 switch (dev_priv->no_fbc_reason) {
675 drm_i915_private_t *dev_priv = dev->dev_private;
695 drm_i915_private_t *dev_priv = dev->dev_private;
698 temp = i915_mch_val(dev_priv);
699 chipset = i915_chipset_val(dev_priv);
700 gfx = i915_gfx_val(dev_priv);
714 drm_i915_private_t *dev_priv = dev->dev_private;
736 drm_i915_private_t *dev_priv = dev->dev_private;
742 atomic_read(&dev_priv->mm.wedged));
754 drm_i915_private_t *dev_priv = dev->dev_private;
771 atomic_set(&dev_priv->mm.wedged, val);
773 DRM_WAKEUP(&dev_priv->irq_queue);
774 queue_work(dev_priv->wq, &dev_priv->error_work);