Lines Matching refs:pvt
388 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
389 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
392 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
393 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
550 struct i7core_pvt *pvt = mci->pvt_info;
559 pdev = pvt->pci_mcr[0];
564 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
565 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
566 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
567 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
570 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
571 pvt->info.max_dod, pvt->info.ch_map);
573 if (ECC_ENABLED(pvt)) {
574 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
575 if (ECCx8(pvt))
586 numdimms(pvt->info.max_dod),
587 numrank(pvt->info.max_dod >> 2),
588 numbank(pvt->info.max_dod >> 4),
589 numrow(pvt->info.max_dod >> 6),
590 numcol(pvt->info.max_dod >> 9));
595 if (!pvt->pci_ch[i][0])
598 if (!CH_ACTIVE(pvt, i)) {
602 if (CH_DISABLED(pvt, i)) {
608 pci_read_config_dword(pvt->pci_ch[i][0],
611 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
620 pci_read_config_dword(pvt->pci_ch[i][1],
622 pci_read_config_dword(pvt->pci_ch[i][1],
624 pci_read_config_dword(pvt->pci_ch[i][1],
630 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
632 pvt->channel[i].ranks,
650 pvt->channel[i].dimms++;
678 pvt->csrow_map[i][j] = *csrow;
732 struct i7core_pvt *pvt = mci->pvt_info;
734 pvt->inject.enable = 0;
736 if (!pvt->pci_ch[pvt->inject.channel][0])
739 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
755 struct i7core_pvt *pvt = mci->pvt_info;
759 if (pvt->inject.enable)
766 pvt->inject.section = (u32) value;
773 struct i7core_pvt *pvt = mci->pvt_info;
774 return sprintf(data, "0x%08x\n", pvt->inject.section);
788 struct i7core_pvt *pvt = mci->pvt_info;
792 if (pvt->inject.enable)
799 pvt->inject.type = (u32) value;
806 struct i7core_pvt *pvt = mci->pvt_info;
807 return sprintf(data, "0x%08x\n", pvt->inject.type);
823 struct i7core_pvt *pvt = mci->pvt_info;
827 if (pvt->inject.enable)
834 pvt->inject.eccmask = (u32) value;
841 struct i7core_pvt *pvt = mci->pvt_info;
842 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
861 struct i7core_pvt *pvt; \
866 pvt = mci->pvt_info; \
868 if (pvt->inject.enable) \
879 pvt->inject.param = value; \
888 struct i7core_pvt *pvt; \
890 pvt = mci->pvt_info; \
891 debugf1("%s() pvt=%p\n", __func__, pvt); \
892 if (pvt->inject.param < 0) \
895 return sprintf(data, "%d\n", pvt->inject.param);\
945 struct i7core_pvt *pvt = mci->pvt_info;
951 if (!pvt->pci_ch[pvt->inject.channel][0])
959 pvt->inject.enable = 1;
965 /* Sets pvt->inject.dimm mask */
966 if (pvt->inject.dimm < 0)
969 if (pvt->channel[pvt->inject.channel].dimms > 2)
970 mask |= (pvt->inject.dimm & 0x3LL) << 35;
972 mask |= (pvt->inject.dimm & 0x1LL) << 36;
975 /* Sets pvt->inject.rank mask */
976 if (pvt->inject.rank < 0)
979 if (pvt->channel[pvt->inject.channel].dimms > 2)
980 mask |= (pvt->inject.rank & 0x1LL) << 34;
982 mask |= (pvt->inject.rank & 0x3LL) << 34;
985 /* Sets pvt->inject.bank mask */
986 if (pvt->inject.bank < 0)
989 mask |= (pvt->inject.bank & 0x15LL) << 30;
991 /* Sets pvt->inject.page mask */
992 if (pvt->inject.page < 0)
995 mask |= (pvt->inject.page & 0xffff) << 14;
997 /* Sets pvt->inject.column mask */
998 if (pvt->inject.col < 0)
1001 mask |= (pvt->inject.col & 0x3fff);
1010 injectmask = (pvt->inject.type & 1) |
1011 (pvt->inject.section & 0x3) << 1 |
1012 (pvt->inject.type & 0x6) << (3 - 1);
1015 pci_write_config_dword(pvt->pci_noncore,
1018 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1020 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1023 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1024 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1026 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1034 pci_write_config_dword(pvt->pci_noncore,
1039 mask, pvt->inject.eccmask, injectmask);
1048 struct i7core_pvt *pvt = mci->pvt_info;
1051 if (!pvt->pci_ch[pvt->inject.channel][0])
1054 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1060 pvt->inject.enable = 1;
1062 return sprintf(data, "%d\n", pvt->inject.enable);
1070 struct i7core_pvt *pvt = mci->pvt_info; \
1073 if (!pvt->ce_count_available || (pvt->is_registered)) \
1076 pvt->udimm_ce_count[param]); \
1386 struct i7core_pvt *pvt = mci->pvt_info;
1391 pvt->i7core_dev = i7core_dev;
1394 pvt->is_registered = 0;
1405 pvt->pci_mcr[func] = pdev;
1409 pvt->pci_ch[slot - 4][func] = pdev;
1411 pvt->pci_noncore = pdev;
1421 pvt->is_registered = 1;
1429 if (!pvt->is_registered)
1449 struct i7core_pvt *pvt = mci->pvt_info;
1450 int row = pvt->csrow_map[chan][dimm], i;
1455 pvt->i7core_dev->socket, chan, dimm);
1465 struct i7core_pvt *pvt = mci->pvt_info;
1468 if (pvt->ce_count_available) {
1471 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1472 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1473 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1477 pvt->rdimm_ce_count[chan][2] += add2;
1481 pvt->rdimm_ce_count[chan][1] += add1;
1485 pvt->rdimm_ce_count[chan][0] += add0;
1487 pvt->ce_count_available = 1;
1490 pvt->rdimm_last_ce_count[chan][2] = new2;
1491 pvt->rdimm_last_ce_count[chan][1] = new1;
1492 pvt->rdimm_last_ce_count[chan][0] = new0;
1506 struct i7core_pvt *pvt = mci->pvt_info;
1511 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1513 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1515 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1517 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1519 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1521 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1527 if (pvt->channel[i].dimms > 2) {
1551 struct i7core_pvt *pvt = mci->pvt_info;
1555 if (!pvt->pci_mcr[4]) {
1561 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1562 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1570 if (pvt->ce_count_available) {
1574 add2 = new2 - pvt->udimm_last_ce_count[2];
1575 add1 = new1 - pvt->udimm_last_ce_count[1];
1576 add0 = new0 - pvt->udimm_last_ce_count[0];
1580 pvt->udimm_ce_count[2] += add2;
1584 pvt->udimm_ce_count[1] += add1;
1588 pvt->udimm_ce_count[0] += add0;
1595 pvt->ce_count_available = 1;
1598 pvt->udimm_last_ce_count[2] = new2;
1599 pvt->udimm_last_ce_count[1] = new1;
1600 pvt->udimm_last_ce_count[0] = new0;
1619 struct i7core_pvt *pvt = mci->pvt_info;
1697 csrow = pvt->csrow_map[channel][dimm];
1703 else if (!pvt->is_registered)
1716 struct i7core_pvt *pvt = mci->pvt_info;
1727 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1732 m = pvt->mce_outentry;
1733 if (pvt->mce_in + count > MCE_LOG_LEN) {
1734 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1736 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1738 pvt->mce_in = 0;
1742 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1744 pvt->mce_in += count;
1747 if (pvt->mce_overrun) {
1749 pvt->mce_overrun);
1751 pvt->mce_overrun = 0;
1758 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1764 if (!pvt->is_registered)
1781 struct i7core_pvt *pvt = mci->pvt_info;
1796 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
1801 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1803 pvt->mce_overrun++;
1808 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1810 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1824 struct i7core_pvt *pvt;
1829 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1839 pvt = mci->pvt_info;
1840 memset(pvt, 0, sizeof(*pvt));
1885 pvt->inject.channel = 0;
1886 pvt->inject.dimm = -1;
1887 pvt->inject.rank = -1;
1888 pvt->inject.bank = -1;
1889 pvt->inject.page = -1;
1890 pvt->inject.col = -1;
1893 pvt->edac_mce.priv = mci;
1894 pvt->edac_mce.check_error = i7core_mce_check_error;
1896 rc = edac_mce_register(&pvt->edac_mce);
1993 struct i7core_pvt *pvt = mci->pvt_info;
1995 i7core_dev = pvt->i7core_dev;
1996 edac_mce_unregister(&pvt->edac_mce);