Lines Matching refs:pvt
448 struct i5400_pvt *pvt;
451 pvt = mci->pvt_info;
454 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
467 pci_read_config_dword(pvt->branchmap_werrors,
469 pci_read_config_word(pvt->branchmap_werrors,
471 pci_read_config_word(pvt->branchmap_werrors,
475 pci_write_config_dword(pvt->branchmap_werrors,
485 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
493 pci_read_config_dword(pvt->branchmap_werrors,
495 pci_read_config_word(pvt->branchmap_werrors,
497 pci_read_config_dword(pvt->branchmap_werrors,
499 pci_read_config_dword(pvt->branchmap_werrors,
503 pci_write_config_dword(pvt->branchmap_werrors,
708 struct i5400_pvt *pvt;
710 pvt = mci->pvt_info;
713 pci_dev_put(pvt->branch_1);
714 pci_dev_put(pvt->branch_0);
715 pci_dev_put(pvt->fsb_error_regs);
716 pci_dev_put(pvt->branchmap_werrors);
727 struct i5400_pvt *pvt;
730 pvt = mci->pvt_info;
731 pvt->branchmap_werrors = NULL;
732 pvt->fsb_error_regs = NULL;
733 pvt->branch_0 = NULL;
734 pvt->branch_1 = NULL;
738 while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
756 pvt->branchmap_werrors = pdev;
759 pvt->fsb_error_regs = pdev;
765 pci_name(pvt->system_address),
766 pvt->system_address->vendor, pvt->system_address->device);
768 pci_name(pvt->branchmap_werrors),
769 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
771 pci_name(pvt->fsb_error_regs),
772 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
774 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
776 if (!pvt->branch_0) {
787 if (pvt->maxch < CHANNELS_PER_BRANCH)
790 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
792 if (!pvt->branch_1) {
822 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
828 amb_present = pvt->b0_ambpresent1;
830 amb_present = pvt->b0_ambpresent0;
833 amb_present = pvt->b1_ambpresent1;
835 amb_present = pvt->b1_ambpresent0;
842 * determine_mtr(pvt, csrow, channel)
846 static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
863 mtr = pvt->b0_mtr[n];
865 mtr = pvt->b1_mtr[n];
894 static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
901 mtr = determine_mtr(pvt, csrow, channel);
903 amb_present_reg = determine_amb_present_reg(pvt, channel);
932 static void calculate_dimm_size(struct i5400_pvt *pvt)
954 max_csrows = pvt->maxdimmperch;
972 for (channel = 0; channel < pvt->maxch; channel++) {
973 dinfo = &pvt->dimm_info[csrow][channel];
974 handle_channel(pvt, csrow, channel, dinfo);
997 for (channel = 0; channel < pvt->maxch; channel++) {
1016 struct i5400_pvt *pvt;
1024 pvt = mci->pvt_info;
1026 pci_read_config_dword(pvt->system_address, AMBASE,
1027 (u32 *) &pvt->ambase);
1028 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1029 ((u32 *) &pvt->ambase) + sizeof(u32));
1031 maxdimmperch = pvt->maxdimmperch;
1032 maxch = pvt->maxch;
1035 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1038 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1039 pvt->tolm >>= 12;
1040 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1041 pvt->tolm);
1043 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1045 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1047 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1048 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1051 limit = (pvt->mir0 >> 4) & 0x0fff;
1052 way0 = pvt->mir0 & 0x1;
1053 way1 = pvt->mir0 & 0x2;
1055 limit = (pvt->mir1 >> 4) & 0xfff;
1056 way0 = pvt->mir1 & 0x1;
1057 way1 = pvt->mir1 & 0x2;
1065 pci_read_config_word(pvt->branch_0, where,
1066 &pvt->b0_mtr[slot_row]);
1069 pvt->b0_mtr[slot_row]);
1071 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1072 pvt->b1_mtr[slot_row] = 0;
1077 pci_read_config_word(pvt->branch_1, where,
1078 &pvt->b1_mtr[slot_row]);
1080 pvt->b1_mtr[slot_row]);
1087 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1089 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1090 &pvt->b0_ambpresent0);
1091 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1092 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1093 &pvt->b0_ambpresent1);
1094 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1097 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1098 pvt->b1_ambpresent0 = 0;
1099 pvt->b1_ambpresent1 = 0;
1104 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1106 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1107 &pvt->b1_ambpresent0);
1109 pvt->b1_ambpresent0);
1110 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1111 &pvt->b1_ambpresent1);
1113 pvt->b1_ambpresent1);
1118 calculate_dimm_size(pvt);
1132 struct i5400_pvt *pvt;
1141 pvt = mci->pvt_info;
1143 channel_count = pvt->maxch;
1144 max_csrows = pvt->maxdimmperch;
1154 mtr = determine_mtr(pvt, csrow, 0);
1167 for (channel = 0; channel < pvt->maxch; channel++)
1168 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1195 struct i5400_pvt *pvt;
1198 pvt = mci->pvt_info;
1201 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1207 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1221 struct i5400_pvt *pvt;
1253 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1262 pvt = mci->pvt_info;
1263 pvt->system_address = pdev; /* Record this device in our private */
1264 pvt->maxch = num_channels;
1265 pvt->maxdimmperch = num_dimms_per_channel;