Lines Matching refs:pvt
397 struct i5000_pvt *pvt;
400 pvt = mci->pvt_info;
403 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
415 pci_read_config_dword(pvt->branchmap_werrors,
417 pci_read_config_word(pvt->branchmap_werrors,
419 pci_read_config_word(pvt->branchmap_werrors,
423 pci_write_config_dword(pvt->branchmap_werrors,
433 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
441 pci_read_config_dword(pvt->branchmap_werrors,
443 pci_read_config_word(pvt->branchmap_werrors,
445 pci_read_config_dword(pvt->branchmap_werrors,
447 pci_read_config_dword(pvt->branchmap_werrors,
451 pci_write_config_dword(pvt->branchmap_werrors,
791 struct i5000_pvt *pvt;
794 pvt = mci->pvt_info;
820 pvt->branchmap_werrors = pdev;
837 pci_dev_put(pvt->branchmap_werrors);
846 pvt->fsb_error_regs = pdev;
849 pci_name(pvt->system_address),
850 pvt->system_address->vendor, pvt->system_address->device);
852 pci_name(pvt->branchmap_werrors),
853 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
855 pci_name(pvt->fsb_error_regs),
856 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
868 pci_dev_put(pvt->branchmap_werrors);
869 pci_dev_put(pvt->fsb_error_regs);
873 pvt->branch_0 = pdev;
878 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
891 pci_dev_put(pvt->branchmap_werrors);
892 pci_dev_put(pvt->fsb_error_regs);
893 pci_dev_put(pvt->branch_0);
897 pvt->branch_1 = pdev;
909 struct i5000_pvt *pvt;
911 pvt = mci->pvt_info;
913 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
914 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
915 pci_dev_put(pvt->branch_0); /* DEV 21 */
918 if (pvt->maxch >= CHANNELS_PER_BRANCH)
919 pci_dev_put(pvt->branch_1); /* DEV 22 */
935 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
941 amb_present = pvt->b0_ambpresent1;
943 amb_present = pvt->b0_ambpresent0;
946 amb_present = pvt->b1_ambpresent1;
948 amb_present = pvt->b1_ambpresent0;
955 * determine_mtr(pvt, csrow, channel)
959 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
964 mtr = pvt->b0_mtr[csrow >> 1];
966 mtr = pvt->b1_mtr[csrow >> 1];
991 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
998 mtr = determine_mtr(pvt, csrow, channel);
1000 amb_present_reg = determine_amb_present_reg(pvt, channel);
1032 static void calculate_dimm_size(struct i5000_pvt *pvt)
1058 max_csrows = pvt->maxdimmperch * 2;
1076 for (channel = 0; channel < pvt->maxch; channel++) {
1077 dinfo = &pvt->dimm_info[csrow][channel];
1078 handle_channel(pvt, csrow, channel, dinfo);
1098 for (channel = 0; channel < pvt->maxch; channel++) {
1120 struct i5000_pvt *pvt;
1128 pvt = mci->pvt_info;
1130 pci_read_config_dword(pvt->system_address, AMBASE,
1131 (u32 *) & pvt->ambase);
1132 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1133 ((u32 *) & pvt->ambase) + sizeof(u32));
1135 maxdimmperch = pvt->maxdimmperch;
1136 maxch = pvt->maxch;
1139 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1142 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1143 pvt->tolm >>= 12;
1144 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1145 pvt->tolm);
1147 actual_tolm = pvt->tolm << 28;
1150 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1151 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1152 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1155 limit = (pvt->mir0 >> 4) & 0x0FFF;
1156 way0 = pvt->mir0 & 0x1;
1157 way1 = pvt->mir0 & 0x2;
1159 limit = (pvt->mir1 >> 4) & 0x0FFF;
1160 way0 = pvt->mir1 & 0x1;
1161 way1 = pvt->mir1 & 0x2;
1163 limit = (pvt->mir2 >> 4) & 0x0FFF;
1164 way0 = pvt->mir2 & 0x1;
1165 way1 = pvt->mir2 & 0x2;
1172 pci_read_config_word(pvt->branch_0, where,
1173 &pvt->b0_mtr[slot_row]);
1176 pvt->b0_mtr[slot_row]);
1178 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1179 pci_read_config_word(pvt->branch_1, where,
1180 &pvt->b1_mtr[slot_row]);
1182 where, pvt->b1_mtr[slot_row]);
1184 pvt->b1_mtr[slot_row] = 0;
1192 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1194 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1195 &pvt->b0_ambpresent0);
1196 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1197 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1198 &pvt->b0_ambpresent1);
1199 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1202 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1203 pvt->b1_ambpresent0 = 0;
1204 pvt->b1_ambpresent1 = 0;
1209 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1211 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1212 &pvt->b1_ambpresent0);
1214 pvt->b1_ambpresent0);
1215 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1216 &pvt->b1_ambpresent1);
1218 pvt->b1_ambpresent1);
1223 calculate_dimm_size(pvt);
1237 struct i5000_pvt *pvt;
1246 pvt = mci->pvt_info;
1248 channel_count = pvt->maxch;
1249 max_csrows = pvt->maxdimmperch * 2;
1259 mtr = pvt->b0_mtr[csrow >> 1];
1260 mtr1 = pvt->b1_mtr[csrow >> 1];
1273 for (channel = 0; channel < pvt->maxch; channel++) {
1274 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1302 struct i5000_pvt *pvt;
1305 pvt = mci->pvt_info;
1308 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1314 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1350 struct i5000_pvt *pvt;
1385 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1395 pvt = mci->pvt_info;
1396 pvt->system_address = pdev; /* Record this device in our private */
1397 pvt->maxch = num_channels;
1398 pvt->maxdimmperch = num_dimms_per_channel;