Lines Matching refs:mci
36 #define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
394 static void i5000_get_error_info(struct mem_ctl_info *mci,
400 pvt = mci->pvt_info;
463 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
469 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
542 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
546 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
552 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
642 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
694 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
738 edac_mc_handle_fbd_ce(mci, 0, 0, msg);
746 static void i5000_process_error_info(struct mem_ctl_info *mci,
751 i5000_process_fatal_error_info(mci, info, handle_errors);
754 i5000_process_nonfatal_error_info(mci, info, handle_errors);
763 static void i5000_clear_error(struct mem_ctl_info *mci)
767 i5000_get_error_info(mci, &info);
774 static void i5000_check_error(struct mem_ctl_info *mci)
777 debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
778 i5000_get_error_info(mci, &info);
779 i5000_process_error_info(mci, &info, 1);
788 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
794 pvt = mci->pvt_info;
907 static void i5000_put_devices(struct mem_ctl_info *mci)
911 pvt = mci->pvt_info;
1118 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1128 pvt = mci->pvt_info;
1228 * the mci control structure with the
1235 static int i5000_init_csrows(struct mem_ctl_info *mci)
1246 pvt = mci->pvt_info;
1254 p_csrow = &mci->csrows[csrow];
1300 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1305 pvt = mci->pvt_info;
1349 struct mem_ctl_info *mci;
1385 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1387 if (mci == NULL)
1390 kobject_get(&mci->edac_mci_kobj);
1391 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
1393 mci->dev = &pdev->dev; /* record ptr to the generic device */
1395 pvt = mci->pvt_info;
1401 if (i5000_get_devices(mci, dev_idx))
1405 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1407 mci->mc_idx = 0;
1408 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1409 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1410 mci->edac_cap = EDAC_FLAG_NONE;
1411 mci->mod_name = "i5000_edac.c";
1412 mci->mod_ver = I5000_REVISION;
1413 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1414 mci->dev_name = pci_name(pdev);
1415 mci->ctl_page_to_phys = NULL;
1418 mci->edac_check = i5000_check_error;
1422 if (i5000_init_csrows(mci)) {
1423 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1426 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1429 i5000_enable_error_reporting(mci);
1433 if (edac_mc_add_mc(mci)) {
1439 i5000_clear_error(mci);
1457 i5000_put_devices(mci);
1460 kobject_put(&mci->edac_mci_kobj);
1461 edac_mc_free(mci);
1494 struct mem_ctl_info *mci;
1501 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1505 i5000_put_devices(mci);
1506 kobject_put(&mci->edac_mci_kobj);
1507 edac_mc_free(mci);