Lines Matching refs:dram
102 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
105 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
1081 static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1084 u32 off = dram << 3; /* 8 bytes between DRAM entries */
1089 pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
1090 pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
1091 pvt->dram_rw_en[dram] = (low & 0x3);
1099 pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
1100 pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
1101 pvt->dram_DstNode[dram] = (low & 0x7);
1289 static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1293 low_offset = K8_DRAM_BASE_LOW + (dram << 3);
1294 high_offset = F10_DRAM_BASE_HIGH + (dram << 3);
1303 pvt->dram_rw_en[dram] = (low_base & 0x3);
1305 if (pvt->dram_rw_en[dram] == 0)
1308 pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
1310 pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
1313 low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
1314 high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
1322 pvt->dram_DstNode[dram] = (low_limit & 0x7);
1323 pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7;
1329 pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
1554 debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
2153 int dram;
2177 for (dram = 0; dram < DRAM_REG_COUNT; dram++) {
2182 pvt->ops->read_dram_base_limit(pvt, dram);
2189 if (pvt->dram_rw_en[dram] != 0) {
2192 dram,
2193 pvt->dram_base[dram],
2194 pvt->dram_limit[dram]);
2198 pvt->dram_IntlvEn[dram] ?
2200 (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W",
2201 (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R",
2202 pvt->dram_IntlvSel[dram],
2203 pvt->dram_DstNode[dram]);