Lines Matching refs:debugf0
984 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
992 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
1002 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
1010 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
1208 debugf0("Data width is not 128 bits - need more decoding\n");
1230 debugf0("MCT channel count: %d\n", channels);
1339 debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
1344 debugf0(" DCT mode: %s, All DCTs on: %s\n",
1349 debugf0(" Address range split per DCT: %s\n",
1352 debugf0(" DCT data interleave for ECC: %s, "
1357 debugf0(" DCT channel interleave: %s, "
1909 debugf0("syndrome(%x) not found\n", syndrome);
2160 debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem);
2166 debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2168 debugf0(" TOP_MEM2 disabled.\n");
2292 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2293 debugf0(" nr_pages= %u channel-count = %d\n",
2314 debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg,
2399 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2472 debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
2501 debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
2753 debugf0("failure to init 2nd stage: ret=%d\n", ret);
2774 debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev),
2784 debugf0("ret=%d\n", ret);