Lines Matching defs:csrow
205 static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
208 return csrow;
210 return csrow >> 1;
214 static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow)
217 return pvt->dcsb0[csrow];
219 return pvt->dcsb1[csrow];
227 static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow)
230 return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)];
232 return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)];
347 * Extract the DRAM CS base address from selected csrow register.
349 static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow)
351 return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) <<
356 * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
358 static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow)
364 dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask;
380 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
385 int csrow;
395 for (csrow = 0; csrow < pvt->cs_count; csrow++) {
398 if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
401 base = base_from_dct_base(pvt, csrow);
402 mask = ~mask_from_dct_mask(pvt, csrow);
405 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
406 (unsigned long)input_addr, csrow,
409 return csrow;
413 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
742 * Find the minimum and maximum InputAddr values that map to the given @csrow.
745 static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
752 BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));
754 base = base_from_dct_base(pvt, csrow);
755 mask = mask_from_dct_mask(pvt, csrow);
774 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
779 int csrow;
781 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
783 if (csrow == -1)
785 "Failed to translate InputAddr to csrow for "
787 return csrow;
925 * To find the max InputAddr for the csrow, start with the base address and set
936 * To find the max InputAddr for the csrow, start with the base address and set
1108 int channel, csrow;
1155 csrow = sys_addr_to_csrow(src_mci, sys_addr);
1156 if (csrow < 0) {
1161 edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow,
1452 * checks if the csrow passed in is marked as SPARED, if so returns the new
1455 static inline int f10_process_possible_spare(int csrow,
1465 if (swap_done && (csrow == bad_dram_cs))
1466 csrow = CH1SPARE_RANK;
1470 if (swap_done && (csrow == bad_dram_cs))
1471 csrow = CH0SPARE_RANK;
1473 return csrow;
1482 * 0..csrow = Chip-Select Row
1490 int csrow;
1500 for (csrow = 0; csrow < pvt->cs_count; csrow++) {
1502 cs_base = amd64_get_dct_base(pvt, cs, csrow);
1517 cs_mask = amd64_get_dct_mask(pvt, cs, csrow);
1520 csrow, cs_base, cs_mask);
1530 cs_found = f10_process_possible_spare(csrow, cs, pvt);
1532 debugf1(" MATCH csrow=%d\n", cs_found);
1660 int nid, csrow, chan = 0;
1663 csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
1665 if (csrow < 0) {
1683 edac_mc_handle_ce(mci, page, offset, syndrome, csrow, chan,
1689 for (chan = 0; chan < mci->csrows[csrow].nr_channels; chan++)
1691 csrow, chan, EDAC_MOD_STR);
2006 int csrow;
2036 csrow = sys_addr_to_csrow(log_mci, sys_addr);
2037 if (csrow < 0) {
2039 "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
2044 edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR);
2292 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2300 * Initialize the array of csrow attribute instances, based on the values
2305 struct csrow_info *csrow;
2320 csrow = &mci->csrows[i];
2332 csrow->nr_pages = amd64_csrow_nr_pages(i, pvt);
2335 csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
2337 csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT);
2338 csrow->page_mask = ~mask_from_dct_mask(pvt, i);
2341 csrow->mtype = amd64_determine_memory_type(pvt);
2343 debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i);
2348 (unsigned long)sys_addr, csrow->page_mask);
2351 (unsigned)csrow->nr_pages,
2352 csrow->first_page, csrow->last_page);
2358 csrow->edac_mode =
2362 csrow->edac_mode = EDAC_NONE;