Lines Matching refs:dst_def_cfg
183 * @dst_def_cfg: Default cfg register setting for dst.
207 u32 dst_def_cfg;
702 writel(d40c->dst_def_cfg,
1510 d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1512 d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1513 d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1515 d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
1616 d40c->dst_def_cfg,
1695 &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1836 d40c->dst_def_cfg,
1974 d40c->dst_def_cfg,