Lines Matching refs:dma_cfg
180 * @dma_cfg: The client configuration of this dma channel.
203 struct stedma40_chan_cfg dma_cfg;
618 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
619 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
620 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
628 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
629 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
646 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
647 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
652 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM)
691 var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
984 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH &&
991 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM &&
1122 bool is_log = (d40c->dma_cfg.channel_type &
1129 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1130 dev_type = d40c->dma_cfg.src_dev_type;
1133 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1134 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1136 dev_type = d40c->dma_cfg.dst_dev_type;
1146 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1217 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1218 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1219 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1224 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1271 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1272 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1273 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1275 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1276 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1328 d40c->dma_cfg.channel_type = 0;
1383 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1384 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
1385 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1386 else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1387 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1433 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1575 d40c->dma_cfg.src_info.data_width,
1585 d40c->dma_cfg.dst_info.data_width,
1604 d40c->dma_cfg.src_info.data_width,
1605 d40c->dma_cfg.src_info.psize,
1617 d40c->dma_cfg.dst_info.data_width,
1618 d40c->dma_cfg.dst_info.psize,
1651 d40c->dma_cfg = *info;
1675 if (d40c->dma_cfg.channel_type == 0) {
1694 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1698 d40_log_cfg(&d40c->dma_cfg,
1701 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1703 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1706 d40c->dma_cfg.dst_dev_type *
1800 d40c->dma_cfg.src_info.data_width,
1808 d40c->dma_cfg.dst_info.data_width,
1822 d40c->dma_cfg.src_info.psize,
1826 d40c->dma_cfg.src_info.data_width,
1834 d40c->dma_cfg.dst_info.psize,
1838 d40c->dma_cfg.dst_info.data_width,
1895 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1900 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1909 d40c->dma_cfg.src_info.data_width,
1910 d40c->dma_cfg.dst_info.data_width,
1947 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1952 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1963 d40c->dma_cfg.src_info.data_width,
1964 d40c->dma_cfg.src_info.psize,
1975 d40c->dma_cfg.dst_info.data_width,
1976 d40c->dma_cfg.dst_info.psize,
2004 if (d40c->dma_cfg.pre_transfer)
2005 d40c->dma_cfg.pre_transfer(chan,
2006 d40c->dma_cfg.pre_transfer_data,
2094 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;