Lines Matching refs:d40d
308 static int d40_pool_lli_alloc(struct d40_desc *d40d,
320 base = d40d->lli_pool.pre_alloc_lli;
321 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
322 d40d->lli_pool.base = NULL;
324 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
326 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
327 d40d->lli_pool.base = base;
329 if (d40d->lli_pool.base == NULL)
334 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
336 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
339 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
341 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
344 d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
345 d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
351 static void d40_pool_lli_free(struct d40_desc *d40d)
353 kfree(d40d->lli_pool.base);
354 d40d->lli_pool.base = NULL;
355 d40d->lli_pool.size = 0;
356 d40d->lli_log.src = NULL;
357 d40d->lli_log.dst = NULL;
358 d40d->lli_phy.src = NULL;
359 d40d->lli_phy.dst = NULL;
360 d40d->lli_phy.src_addr = 0;
361 d40d->lli_phy.dst_addr = 0;
378 static void d40_desc_remove(struct d40_desc *d40d)
380 list_del(&d40d->node);
405 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
407 kmem_cache_free(d40c->base->desc_slab, d40d);
569 struct d40_desc *d40d;
573 while ((d40d = d40_first_active_get(d40c))) {
574 d40_desc_remove(d40d);
577 d40_desc_free(d40c, d40d);
581 while ((d40d = d40_first_queued(d40c))) {
582 d40_desc_remove(d40d);
585 d40_desc_free(d40c, d40d);
712 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
714 if (d40d->lli_phy.dst && d40d->lli_phy.src) {
717 d40d->lli_phy.dst,
718 d40d->lli_phy.src);
719 } else if (d40d->lli_log.dst && d40d->lli_log.src) {
720 struct d40_log_lli *src = d40d->lli_log.src;
721 struct d40_log_lli *dst = d40d->lli_log.dst;
724 src += d40d->lli_count;
725 dst += d40d->lli_count;
741 d40d->lli_count += d40d->lli_tx_len;
749 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
754 tx->cookie = d40_assign_cookie(d40c, d40d);
756 d40_desc_queue(d40c, d40d);
784 struct d40_desc *d40d;
788 d40d = d40_first_queued(d40c);
790 if (d40d != NULL) {
794 d40_desc_remove(d40d);
797 d40_desc_submit(d40c, d40d);
800 d40_desc_load(d40c, d40d);
809 return d40d;
815 struct d40_desc *d40d;
821 d40d = d40_first_active_get(d40c);
823 if (d40d == NULL)
826 if (d40d->lli_count < d40d->lli_len) {
828 d40_desc_load(d40c, d40d);
1530 struct d40_desc *d40d;
1542 d40d = d40_desc_get(d40c);
1544 if (d40d == NULL)
1547 d40d->lli_len = sgl_len;
1548 d40d->lli_tx_len = d40d->lli_len;
1549 d40d->txd.flags = dma_flags;
1552 if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
1553 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1562 d40d->lli_tx_len = 1;
1564 if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
1573 d40d->lli_log.src,
1577 d40d->lli_tx_len,
1583 d40d->lli_log.dst,
1587 d40d->lli_tx_len,
1592 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1601 d40d->lli_phy.src,
1602 d40d->lli_phy.src_addr,
1614 d40d->lli_phy.dst,
1615 d40d->lli_phy.dst_addr,
1624 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1625 d40d->lli_pool.size, DMA_TO_DEVICE);
1628 dma_async_tx_descriptor_init(&d40d->txd, chan);
1630 d40d->txd.tx_submit = d40_tx_submit;
1634 return &d40d->txd;
1758 struct d40_desc *d40d;
1771 d40d = d40_desc_get(d40c);
1773 if (d40d == NULL) {
1779 d40d->txd.flags = dma_flags;
1781 dma_async_tx_descriptor_init(&d40d->txd, chan);
1783 d40d->txd.tx_submit = d40_tx_submit;
1787 if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
1792 d40d->lli_len = 1;
1793 d40d->lli_tx_len = 1;
1795 d40_log_fill_lli(d40d->lli_log.src,
1803 d40_log_fill_lli(d40d->lli_log.dst,
1813 if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
1819 err = d40_phy_fill_lli(d40d->lli_phy.src,
1831 err = d40_phy_fill_lli(d40d->lli_phy.dst,
1844 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1845 d40d->lli_pool.size, DMA_TO_DEVICE);
1849 return &d40d->txd;
1854 d40_pool_lli_free(d40d);
1860 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1870 if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
1876 d40d->lli_len = sg_len;
1877 if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
1878 d40d->lli_tx_len = d40d->lli_len;
1880 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1889 d40d->lli_tx_len = 1;
1907 &d40d->lli_log,
1913 dev_addr, d40d->lli_tx_len,
1922 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1933 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1939 d40d->lli_len = sgl_len;
1940 d40d->lli_tx_len = sgl_len;
1960 d40d->lli_phy.src,
1961 d40d->lli_phy.src_addr,
1972 d40d->lli_phy.dst,
1973 d40d->lli_phy.dst_addr,
1981 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1982 d40d->lli_pool.size, DMA_TO_DEVICE);
1992 struct d40_desc *d40d;
2010 d40d = d40_desc_get(d40c);
2013 if (d40d == NULL)
2017 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2020 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2030 d40d->txd.flags = dma_flags;
2032 dma_async_tx_descriptor_init(&d40d->txd, chan);
2034 d40d->txd.tx_submit = d40_tx_submit;
2036 return &d40d->txd;