Lines Matching refs:sw_desc
2224 struct ppc440spe_adma_desc_slot *sw_desc;
2231 sw_desc = tx_to_ppc440spe_adma_slot(tx);
2233 group_start = sw_desc->group_head;
2239 cookie = ppc440spe_desc_assign_cookie(chan, sw_desc);
2243 list_splice_init(&sw_desc->group_list, &chan->chain);
2250 list_splice_init(&sw_desc->group_list,
2264 sw_desc->async_tx.cookie, sw_desc->idx, sw_desc);
2276 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
2287 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2289 if (sw_desc) {
2290 group_start = sw_desc->group_head;
2293 sw_desc->async_tx.flags = flags;
2297 return sw_desc ? &sw_desc->async_tx : NULL;
2308 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
2325 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2327 if (sw_desc) {
2328 group_start = sw_desc->group_head;
2333 sw_desc->unmap_len = len;
2334 sw_desc->async_tx.flags = flags;
2338 return sw_desc ? &sw_desc->async_tx : NULL;
2349 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
2367 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2369 if (sw_desc) {
2370 group_start = sw_desc->group_head;
2374 sw_desc->unmap_len = len;
2375 sw_desc->async_tx.flags = flags;
2379 return sw_desc ? &sw_desc->async_tx : NULL;
2391 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
2409 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2411 if (sw_desc) {
2412 group_start = sw_desc->group_head;
2419 sw_desc->unmap_len = len;
2420 sw_desc->async_tx.flags = flags;
2424 return sw_desc ? &sw_desc->async_tx : NULL;
2457 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2467 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2468 if (sw_desc) {
2473 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2474 set_bits(op, &sw_desc->flags);
2475 sw_desc->src_cnt = src_cnt;
2476 sw_desc->dst_cnt = dst_cnt;
2480 iter = list_first_entry(&sw_desc->group_list,
2525 sw_desc->async_tx.flags = flags;
2530 return sw_desc;
2543 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2553 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2554 if (sw_desc) {
2559 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2560 set_bits(op, &sw_desc->flags);
2561 sw_desc->src_cnt = src_cnt;
2562 sw_desc->dst_cnt = 1;
2564 iter = list_first_entry(&sw_desc->group_list,
2634 sw_desc->async_tx.flags = flags;
2639 return sw_desc;
2648 struct ppc440spe_adma_desc_slot *sw_desc = NULL, *iter;
2748 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2749 if (sw_desc) {
2750 ppc440spe_desc_init_dma01pq(sw_desc, dst_cnt, src_cnt,
2756 ppc440spe_adma_pq_set_dest(sw_desc, dst, flags);
2758 ppc440spe_adma_pq_set_src(sw_desc, src[src_cnt],
2769 ppc440spe_adma_pq_set_src_mult(sw_desc,
2774 sw_desc->async_tx.flags = flags;
2775 list_for_each_entry(iter, &sw_desc->group_list,
2784 return sw_desc;
2793 struct ppc440spe_adma_desc_slot *sw_desc = NULL, *iter;
2811 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2812 if (sw_desc) {
2814 sw_desc->async_tx.flags = flags;
2815 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
2827 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
2833 &sw_desc->group_list))) {
2847 sw_desc->dst_cnt = dst_cnt;
2849 set_bit(PPC440SPE_ZERO_P, &sw_desc->flags);
2851 set_bit(PPC440SPE_ZERO_Q, &sw_desc->flags);
2854 ppc440spe_adma_pq_set_dest(sw_desc, dst, flags);
2860 ppc440spe_adma_pq_set_src(sw_desc, src[src_cnt],
2864 ppc440spe_adma_pq_set_src_mult(sw_desc,
2870 return sw_desc;
2882 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2900 sw_desc = ppc440spe_dma01_prep_mult(ppc440spe_chan,
2902 return sw_desc ? &sw_desc->async_tx : NULL;
2906 sw_desc = ppc440spe_dma01_prep_sum_product(ppc440spe_chan,
2908 return sw_desc ? &sw_desc->async_tx : NULL;
2933 sw_desc = ppc440spe_dma01_prep_pq(ppc440spe_chan,
2939 sw_desc = ppc440spe_dma2_prep_pq(ppc440spe_chan,
2945 return sw_desc ? &sw_desc->async_tx : NULL;
2958 struct ppc440spe_adma_desc_slot *sw_desc, *iter;
2989 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2991 if (sw_desc) {
2992 ppc440spe_desc_init_dma01pqzero_sum(sw_desc, dst_cnt, src_cnt);
2995 sw_desc->async_tx.flags = flags;
2996 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
3006 iter = sw_desc->group_head;
3029 iter = list_first_entry(&sw_desc->group_list,
3059 ppc440spe_adma_pqzero_sum_set_dest(sw_desc, pdest, qdest);
3063 list_for_each_entry_reverse(iter, &sw_desc->group_list,
3102 list_for_each_entry_continue_reverse(iter, &sw_desc->group_list,
3124 return sw_desc ? &sw_desc->async_tx : NULL;
3152 static void ppc440spe_adma_set_dest(struct ppc440spe_adma_desc_slot *sw_desc,
3157 BUG_ON(index >= sw_desc->dst_cnt);
3159 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3167 ppc440spe_desc_set_dest_addr(sw_desc->group_head,
3171 sw_desc = ppc440spe_get_group_entry(sw_desc, index);
3172 ppc440spe_desc_set_dest_addr(sw_desc,
3199 static void ppc440spe_adma_pq_set_dest(struct ppc440spe_adma_desc_slot *sw_desc,
3208 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3229 if (!test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
3231 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
3233 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
3236 iter = ppc440spe_get_group_entry(sw_desc, index);
3240 &sw_desc->group_list, chain_node)
3246 &sw_desc->group_list, chain_node) {
3260 &sw_desc->flags)) {
3262 sw_desc, index++);
3268 &sw_desc->flags)) {
3270 sw_desc, index++);
3283 ppath = test_bit(PPC440SPE_ZERO_P, &sw_desc->flags) ?
3287 qpath = test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags) ?
3293 iter = ppc440spe_get_group_entry(sw_desc, index++);
3299 iter = ppc440spe_get_group_entry(sw_desc,
3305 if (test_bit(PPC440SPE_DESC_WXOR, &sw_desc->flags)) {
3309 iter = ppc440spe_get_group_entry(sw_desc,
3314 &sw_desc->group_list,
3324 &sw_desc->group_list,
3347 ppath = test_bit(PPC440SPE_ZERO_P, &sw_desc->flags) ?
3352 qpath = test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags) ?
3357 iter = ppc440spe_get_group_entry(sw_desc, 0);
3358 for (i = 0; i < sw_desc->descs_per_op; i++) {
3369 iter = ppc440spe_get_group_entry(sw_desc,
3370 sw_desc->descs_per_op);
3371 for (i = 0; i < sw_desc->descs_per_op; i++) {
3389 struct ppc440spe_adma_desc_slot *sw_desc,
3397 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3404 list_for_each_entry_reverse(end, &sw_desc->group_list,
3411 iter = ppc440spe_get_group_entry(sw_desc, idx);
3415 list_for_each_entry_from(iter, &sw_desc->group_list,
3427 list_for_each_entry_from(iter, &sw_desc->group_list,
3465 static void ppc440spe_adma_pq_set_src(struct ppc440spe_adma_desc_slot *sw_desc,
3472 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3479 if (test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
3482 &sw_desc->flags) ? 2 : 3;
3490 &sw_desc->flags))
3494 &sw_desc->flags))
3498 &sw_desc->flags))
3502 &sw_desc->flags))
3508 iter = ppc440spe_get_group_entry(sw_desc, 0);
3520 iter = ppc440spe_get_group_entry(sw_desc,
3521 index - iskip + sw_desc->dst_cnt);
3529 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
3531 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
3535 iter = ppc440spe_get_group_entry(sw_desc,
3543 test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags) &&
3544 sw_desc->dst_cnt == 2) {
3548 iter = ppc440spe_get_group_entry(sw_desc, 1);
3557 iter = sw_desc->group_head;
3563 iter = ppc440spe_get_group_entry(sw_desc,
3564 sw_desc->descs_per_op);
3575 struct ppc440spe_adma_desc_slot *sw_desc,
3580 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3581 sw_desc = sw_desc->group_head;
3583 if (likely(sw_desc))
3584 ppc440spe_desc_set_src_addr(sw_desc, chan, index, 0, addr);
3817 struct ppc440spe_adma_desc_slot *sw_desc,
3824 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3829 if (test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
3831 &sw_desc->flags) ? 2 : 3;
3835 iter = ppc440spe_get_group_entry(sw_desc,
3836 sw_desc->dst_cnt - 1);
3837 if (sw_desc->dst_cnt == 2)
3839 sw_desc, 0);
3845 iter = ppc440spe_get_group_entry(sw_desc,
3847 sw_desc->dst_cnt);
3859 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
3861 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
3864 iter = ppc440spe_get_group_entry(sw_desc, index + znum);
3885 iter = sw_desc->group_head;
3886 if (sw_desc->dst_cnt == 2) {
3891 iter = ppc440spe_get_group_entry(sw_desc,
3892 sw_desc->descs_per_op);
4037 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
4046 sw_desc = ppc440spe_adma_alloc_slots(chan, slot_cnt, slots_per_op);
4047 if (sw_desc) {
4048 group_start = sw_desc->group_head;
4049 list_splice_init(&sw_desc->group_list, &chan->chain);
4050 async_tx_ack(&sw_desc->async_tx);
4062 chan->common.cookie = sw_desc->async_tx.cookie = cookie;
4068 ppc440spe_chan_set_first_xor_descriptor(chan, sw_desc);
4087 struct ppc440spe_adma_desc_slot *sw_desc, *iter;
4101 sw_desc = ppc440spe_adma_alloc_slots(chan, 1, 1);
4102 if (sw_desc) {
4104 ppc440spe_desc_init_dma01pq(sw_desc, 1, 1, 1, op);
4105 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
4122 ppc440spe_adma_pq_set_src(sw_desc, dma_addr, 0);
4123 ppc440spe_adma_pq_set_src_mult(sw_desc, 1, 0, 0);
4126 ppc440spe_adma_pq_set_dest(sw_desc, addrs, DMA_PREP_PQ_DISABLE_Q);
4128 async_tx_ack(&sw_desc->async_tx);
4129 sw_desc->async_tx.callback = ppc440spe_test_callback;
4130 sw_desc->async_tx.callback_param = NULL;
4134 ppc440spe_adma_tx_submit(&sw_desc->async_tx);