Lines Matching refs:adev
66 [PPC_ADMA_INIT_ALLOC] = "failed to allocate memory for adev "
4153 static void ppc440spe_adma_init_capabilities(struct ppc440spe_adma_device *adev)
4155 switch (adev->id) {
4158 dma_cap_set(DMA_MEMCPY, adev->common.cap_mask);
4159 dma_cap_set(DMA_INTERRUPT, adev->common.cap_mask);
4160 dma_cap_set(DMA_MEMSET, adev->common.cap_mask);
4161 dma_cap_set(DMA_PQ, adev->common.cap_mask);
4162 dma_cap_set(DMA_PQ_VAL, adev->common.cap_mask);
4163 dma_cap_set(DMA_XOR_VAL, adev->common.cap_mask);
4166 dma_cap_set(DMA_XOR, adev->common.cap_mask);
4167 dma_cap_set(DMA_PQ, adev->common.cap_mask);
4168 dma_cap_set(DMA_INTERRUPT, adev->common.cap_mask);
4169 adev->common.cap_mask = adev->common.cap_mask;
4174 adev->common.device_alloc_chan_resources =
4176 adev->common.device_free_chan_resources =
4178 adev->common.device_tx_status = ppc440spe_adma_tx_status;
4179 adev->common.device_issue_pending = ppc440spe_adma_issue_pending;
4182 if (dma_has_cap(DMA_MEMCPY, adev->common.cap_mask)) {
4183 adev->common.device_prep_dma_memcpy =
4186 if (dma_has_cap(DMA_MEMSET, adev->common.cap_mask)) {
4187 adev->common.device_prep_dma_memset =
4190 if (dma_has_cap(DMA_XOR, adev->common.cap_mask)) {
4191 adev->common.max_xor = XOR_MAX_OPS;
4192 adev->common.device_prep_dma_xor =
4195 if (dma_has_cap(DMA_PQ, adev->common.cap_mask)) {
4196 switch (adev->id) {
4198 dma_set_maxpq(&adev->common,
4202 dma_set_maxpq(&adev->common,
4206 adev->common.max_pq = XOR_MAX_OPS * 3;
4209 adev->common.device_prep_dma_pq =
4212 if (dma_has_cap(DMA_PQ_VAL, adev->common.cap_mask)) {
4213 switch (adev->id) {
4215 adev->common.max_pq = DMA0_FIFO_SIZE /
4219 adev->common.max_pq = DMA1_FIFO_SIZE /
4223 adev->common.device_prep_dma_pq_val =
4226 if (dma_has_cap(DMA_XOR_VAL, adev->common.cap_mask)) {
4227 switch (adev->id) {
4229 adev->common.max_xor = DMA0_FIFO_SIZE /
4233 adev->common.max_xor = DMA1_FIFO_SIZE /
4237 adev->common.device_prep_dma_xor_val =
4240 if (dma_has_cap(DMA_INTERRUPT, adev->common.cap_mask)) {
4241 adev->common.device_prep_dma_interrupt =
4246 dev_name(adev->dev),
4247 dma_has_cap(DMA_PQ, adev->common.cap_mask) ? "pq " : "",
4248 dma_has_cap(DMA_PQ_VAL, adev->common.cap_mask) ? "pq_val " : "",
4249 dma_has_cap(DMA_XOR, adev->common.cap_mask) ? "xor " : "",
4250 dma_has_cap(DMA_XOR_VAL, adev->common.cap_mask) ? "xor_val " : "",
4251 dma_has_cap(DMA_MEMCPY, adev->common.cap_mask) ? "memcpy " : "",
4252 dma_has_cap(DMA_MEMSET, adev->common.cap_mask) ? "memset " : "",
4253 dma_has_cap(DMA_INTERRUPT, adev->common.cap_mask) ? "intr " : "");
4256 static int ppc440spe_adma_setup_irqs(struct ppc440spe_adma_device *adev,
4264 ofdev = container_of(adev->dev, struct platform_device, dev);
4266 if (adev->id != PPC440SPE_XOR_ID) {
4267 adev->err_irq = irq_of_parse_and_map(np, 1);
4268 if (adev->err_irq == NO_IRQ) {
4269 dev_warn(adev->dev, "no err irq resource?\n");
4271 adev->err_irq = -ENXIO;
4275 adev->err_irq = -ENXIO;
4278 adev->irq = irq_of_parse_and_map(np, 0);
4279 if (adev->irq == NO_IRQ) {
4280 dev_err(adev->dev, "no irq resource\n");
4285 dev_dbg(adev->dev, "irq %d, err irq %d\n",
4286 adev->irq, adev->err_irq);
4288 ret = request_irq(adev->irq, ppc440spe_adma_eot_handler,
4289 0, dev_driver_string(adev->dev), chan);
4291 dev_err(adev->dev, "can't request irq %d\n",
4292 adev->irq);
4301 if (adev->err_irq > 0) {
4303 ret = request_irq(adev->err_irq,
4306 dev_driver_string(adev->dev),
4309 dev_err(adev->dev, "can't request irq %d\n",
4310 adev->err_irq);
4317 if (adev->id == PPC440SPE_XOR_ID) {
4321 &adev->xor_reg->ier);
4332 adev->i2o_reg = of_iomap(np, 0);
4333 if (!adev->i2o_reg) {
4343 enable = (adev->id == PPC440SPE_DMA0_ID) ?
4346 mask = ioread32(&adev->i2o_reg->iopim) & enable;
4347 iowrite32(mask, &adev->i2o_reg->iopim);
4352 free_irq(adev->irq, chan);
4354 irq_dispose_mapping(adev->irq);
4356 if (adev->err_irq > 0) {
4358 irq_dispose_mapping(adev->err_irq);
4363 static void ppc440spe_adma_release_irqs(struct ppc440spe_adma_device *adev,
4368 if (adev->id == PPC440SPE_XOR_ID) {
4370 mask = ioread32be(&adev->xor_reg->ier);
4373 iowrite32be(mask, &adev->xor_reg->ier);
4376 disable = (adev->id == PPC440SPE_DMA0_ID) ?
4379 mask = ioread32(&adev->i2o_reg->iopim) | disable;
4380 iowrite32(mask, &adev->i2o_reg->iopim);
4382 free_irq(adev->irq, chan);
4383 irq_dispose_mapping(adev->irq);
4384 if (adev->err_irq > 0) {
4385 free_irq(adev->err_irq, chan);
4387 irq_dispose_mapping(adev->err_irq);
4388 iounmap(adev->i2o_reg);
4401 struct ppc440spe_adma_device *adev;
4461 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
4462 if (!adev) {
4469 adev->id = id;
4470 adev->pool_size = pool_size;
4472 adev->dma_desc_pool_virt = dma_alloc_coherent(&ofdev->dev,
4473 adev->pool_size, &adev->dma_desc_pool,
4475 if (adev->dma_desc_pool_virt == NULL) {
4478 adev->pool_size);
4484 adev->dma_desc_pool_virt, (u64)adev->dma_desc_pool);
4492 if (adev->id == PPC440SPE_XOR_ID) {
4493 adev->xor_reg = regs;
4495 iowrite32be(XOR_CRSR_XASR_BIT, &adev->xor_reg->crsr);
4496 iowrite32be(XOR_CRSR_64BA_BIT, &adev->xor_reg->crrr);
4498 size_t fifo_size = (adev->id == PPC440SPE_DMA0_ID) ?
4500 adev->dma_reg = regs;
4507 &adev->dma_reg->fsiz);
4510 &adev->dma_reg->cfg);
4512 iowrite32(~0, &adev->dma_reg->dsts);
4515 adev->dev = &ofdev->dev;
4516 adev->common.dev = &ofdev->dev;
4517 INIT_LIST_HEAD(&adev->common.channels);
4518 dev_set_drvdata(&ofdev->dev, adev);
4532 chan->device = adev;
4533 chan->common.device = &adev->common;
4534 list_add_tail(&chan->common.device_node, &adev->common.channels);
4541 if (adev->id != PPC440SPE_XOR_ID) {
4570 ret = ppc440spe_adma_setup_irqs(adev, chan, &initcode);
4574 ppc440spe_adma_init_capabilities(adev);
4576 ret = dma_async_device_register(&adev->common);
4586 ppc440spe_adma_release_irqs(adev, chan);
4595 if (adev->id != PPC440SPE_XOR_ID) {
4606 if (adev->id == PPC440SPE_XOR_ID)
4607 iounmap(adev->xor_reg);
4609 iounmap(adev->dma_reg);
4611 dma_free_coherent(adev->dev, adev->pool_size,
4612 adev->dma_desc_pool_virt,
4613 adev->dma_desc_pool);
4615 kfree(adev);
4630 struct ppc440spe_adma_device *adev = dev_get_drvdata(&ofdev->dev);
4638 if (adev->id < PPC440SPE_ADMA_ENGINES_NUM)
4639 ppc440spe_adma_devices[adev->id] = -1;
4641 dma_async_device_unregister(&adev->common);
4643 list_for_each_entry_safe(chan, _chan, &adev->common.channels,
4646 ppc440spe_adma_release_irqs(adev, ppc440spe_chan);
4648 if (adev->id != PPC440SPE_XOR_ID) {
4668 dma_free_coherent(adev->dev, adev->pool_size,
4669 adev->dma_desc_pool_virt, adev->dma_desc_pool);
4670 if (adev->id == PPC440SPE_XOR_ID)
4671 iounmap(adev->xor_reg);
4673 iounmap(adev->dma_reg);
4676 kfree(adev);