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  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/dma/

Lines Matching refs:cohc

27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
81 static void coh901318_list_print(struct coh901318_chan *cohc,
88 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
194 cohc_dev_addr(struct coh901318_chan *cohc)
197 if (cohc->runtime_addr)
198 return cohc->runtime_addr;
199 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
203 cohc_chan_param(struct coh901318_chan *cohc)
205 return &cohc->base->platform->chan_conf[cohc->id].param;
209 cohc_chan_conf(struct coh901318_chan *cohc)
211 return &cohc->base->platform->chan_conf[cohc->id];
214 static void enable_powersave(struct coh901318_chan *cohc)
217 struct powersave *pm = &cohc->base->pm;
221 pm->started_channels &= ~(1ULL << cohc->id);
225 cohc->base->platform->access_memory_state(cohc->base->dev,
231 static void disable_powersave(struct coh901318_chan *cohc)
234 struct powersave *pm = &cohc->base->pm;
240 cohc->base->platform->access_memory_state(cohc->base->dev,
244 pm->started_channels |= (1ULL << cohc->id);
249 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
251 int channel = cohc->id;
252 void __iomem *virtbase = cohc->base->virtbase;
260 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
262 int channel = cohc->id;
263 void __iomem *virtbase = cohc->base->virtbase;
272 static int coh901318_start(struct coh901318_chan *cohc)
275 int channel = cohc->id;
276 void __iomem *virtbase = cohc->base->virtbase;
278 disable_powersave(cohc);
291 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
294 int channel = cohc->id;
295 void __iomem *virtbase = cohc->base->virtbase;
318 coh901318_assign_cookie(struct coh901318_chan *cohc,
321 dma_cookie_t cookie = cohc->chan.cookie;
326 cohc->chan.cookie = cookie;
333 coh901318_desc_get(struct coh901318_chan *cohc)
337 if (list_empty(&cohc->free)) {
346 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
349 desc = list_first_entry(&cohc->free,
365 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
367 list_add_tail(&cohd->node, &cohc->free);
372 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
374 list_add_tail(&desc->node, &cohc->active);
378 coh901318_first_active_get(struct coh901318_chan *cohc)
382 if (list_empty(&cohc->active))
385 d = list_first_entry(&cohc->active,
398 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
400 list_add_tail(&desc->node, &cohc->queue);
404 coh901318_first_queued(struct coh901318_chan *cohc)
408 if (list_empty(&cohc->queue))
411 d = list_first_entry(&cohc->queue,
437 struct coh901318_chan *cohc = to_coh901318_chan(chan);
444 spin_lock_irqsave(&cohc->lock, flags);
451 list_for_each(pos, &cohc->active) {
465 left = readl(cohc->base->virtbase +
467 COH901318_CX_CTRL_SPACING * cohc->id) &
471 ladd = readl(cohc->base->virtbase +
474 cohc->id) &
503 list_for_each(pos, &cohc->queue) {
508 spin_unlock_irqrestore(&cohc->lock, flags);
521 struct coh901318_chan *cohc = to_coh901318_chan(chan);
522 int channel = cohc->id;
523 void __iomem *virtbase = cohc->base->virtbase;
525 spin_lock_irqsave(&cohc->lock, flags);
534 cohc->stopped = 1;
551 cohc->stopped = 1;
553 enable_powersave(cohc);
555 spin_unlock_irqrestore(&cohc->lock, flags);
565 struct coh901318_chan *cohc = to_coh901318_chan(chan);
566 int channel = cohc->id;
568 spin_lock_irqsave(&cohc->lock, flags);
570 disable_powersave(cohc);
572 if (cohc->stopped) {
574 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
579 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
582 cohc->stopped = 0;
585 spin_unlock_irqrestore(&cohc->lock, flags);
602 static int coh901318_config(struct coh901318_chan *cohc,
607 int channel = cohc->id;
608 void __iomem *virtbase = cohc->base->virtbase;
610 spin_lock_irqsave(&cohc->lock, flags);
615 p = &cohc->base->platform->chan_conf[channel].param;
628 coh901318_set_conf(cohc, p->config);
629 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
631 spin_unlock_irqrestore(&cohc->lock, flags);
643 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
651 cohd = coh901318_first_queued(cohc);
657 cohc->busy = 1;
659 coh901318_desc_submit(cohc, cohd);
661 coh901318_prep_linked_list(cohc, cohd->lli);
664 coh901318_start(cohc);
677 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
683 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
685 cohc->id, cohc->nbr_active_done);
687 spin_lock_irqsave(&cohc->lock, flags);
690 cohd_fin = coh901318_first_active_get(cohc);
700 cohc->completed = cohd_fin->desc.cookie;
703 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
707 coh901318_desc_free(cohc, cohd_fin);
709 spin_unlock_irqrestore(&cohc->lock, flags);
715 spin_lock_irqsave(&cohc->lock, flags);
724 cohc->nbr_active_done--;
725 if (cohc->nbr_active_done) {
726 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
728 if (cohc_chan_conf(cohc)->priority_high)
729 tasklet_hi_schedule(&cohc->tasklet);
731 tasklet_schedule(&cohc->tasklet);
734 spin_unlock_irqrestore(&cohc->lock, flags);
739 spin_unlock_irqrestore(&cohc->lock, flags);
740 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
745 static void dma_tc_handle(struct coh901318_chan *cohc)
751 if (!cohc->allocated) {
752 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
757 spin_lock(&cohc->lock);
761 * should have been moved over from cohc->queue to
762 * cohc->active and run to completion, that is why we're
768 BUG_ON(list_empty(&cohc->active));
770 cohc->nbr_active_done++;
773 * This attempt to take a job from cohc->queue, put it
774 * into cohc->active and start it.
776 if (coh901318_queue_start(cohc) == NULL)
777 cohc->busy = 0;
779 spin_unlock(&cohc->lock);
782 * This tasklet will remove items from cohc->active
785 if (cohc_chan_conf(cohc)->priority_high)
786 tasklet_hi_schedule(&cohc->tasklet);
788 tasklet_schedule(&cohc->tasklet);
799 struct coh901318_chan *cohc;
819 cohc = &base->chans[ch];
820 spin_lock(&cohc->lock);
826 dev_crit(COHC_2_DEV(cohc),
835 dev_warn(COHC_2_DEV(cohc),
845 enable_powersave(cohc);
854 dma_tc_handle(cohc);
857 spin_unlock(&cohc->lock);
865 cohc = &base->chans[ch];
866 spin_lock(&cohc->lock);
872 dev_crit(COHC_2_DEV(cohc),
881 dev_warn(COHC_2_DEV(cohc),
891 enable_powersave(cohc);
899 dma_tc_handle(cohc);
902 spin_unlock(&cohc->lock);
910 struct coh901318_chan *cohc = to_coh901318_chan(chan);
913 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
914 __func__, cohc->id);
919 spin_lock_irqsave(&cohc->lock, flags);
921 coh901318_config(cohc, NULL);
923 cohc->allocated = 1;
924 cohc->completed = chan->cookie = 1;
926 spin_unlock_irqrestore(&cohc->lock, flags);
934 struct coh901318_chan *cohc = to_coh901318_chan(chan);
935 int channel = cohc->id;
938 spin_lock_irqsave(&cohc->lock, flags);
941 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
943 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
946 cohc->allocated = 0;
948 spin_unlock_irqrestore(&cohc->lock, flags);
959 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
962 spin_lock_irqsave(&cohc->lock, flags);
964 tx->cookie = coh901318_assign_cookie(cohc, cohd);
966 coh901318_desc_queue(cohc, cohd);
968 spin_unlock_irqrestore(&cohc->lock, flags);
980 struct coh901318_chan *cohc = to_coh901318_chan(chan);
982 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
985 spin_lock_irqsave(&cohc->lock, flg);
987 dev_vdbg(COHC_2_DEV(cohc),
989 __func__, cohc->id, src, dest, size);
999 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
1005 &cohc->base->pool, lli, src, size, dest,
1006 cohc_chan_param(cohc)->ctrl_lli_chained,
1011 COH_DBG(coh901318_list_print(cohc, lli));
1014 cohd = coh901318_desc_get(cohc);
1019 spin_unlock_irqrestore(&cohc->lock, flg);
1023 spin_unlock_irqrestore(&cohc->lock, flg);
1032 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1040 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1041 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1042 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1052 spin_lock_irqsave(&cohc->lock, flg);
1054 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1061 params = cohc_chan_param(cohc);
1068 ctrl_chained |= cohc->runtime_ctrl;
1069 ctrl_last |= cohc->runtime_ctrl;
1070 ctrl |= cohc->runtime_ctrl;
1091 coh901318_set_conf(cohc, config);
1114 lli = coh901318_lli_alloc(&cohc->base->pool, len);
1120 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1121 cohc_dev_addr(cohc),
1133 coh901318_set_ctrl(cohc, lli->control);
1135 COH_DBG(coh901318_list_print(cohc, lli));
1138 cohd = coh901318_desc_get(cohc);
1144 spin_unlock_irqrestore(&cohc->lock, flg);
1150 spin_unlock_irqrestore(&cohc->lock, flg);
1159 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1164 last_complete = cohc->completed;
1171 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1180 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1183 spin_lock_irqsave(&cohc->lock, flags);
1191 if (!cohc->busy)
1192 coh901318_queue_start(cohc);
1194 spin_unlock_irqrestore(&cohc->lock, flags);
1261 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1278 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1282 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1323 dev_err(COHC_2_DEV(cohc),
1329 dev_dbg(COHC_2_DEV(cohc),
1333 cohc->runtime_addr = addr;
1334 cohc->runtime_ctrl = runtime_ctrl;
1342 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1344 void __iomem *virtbase = cohc->base->virtbase;
1369 spin_lock_irqsave(&cohc->lock, flags);
1372 if (cohc->id < 32) {
1373 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1374 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1376 writel(1 << (cohc->id - 32), virtbase +
1378 writel(1 << (cohc->id - 32), virtbase +
1382 enable_powersave(cohc);
1384 while ((cohd = coh901318_first_active_get(cohc))) {
1386 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1390 coh901318_desc_free(cohc, cohd);
1393 while ((cohd = coh901318_first_queued(cohc))) {
1395 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1399 coh901318_desc_free(cohc, cohd);
1403 cohc->nbr_active_done = 0;
1404 cohc->busy = 0;
1406 spin_unlock_irqrestore(&cohc->lock, flags);
1416 struct coh901318_chan *cohc;
1422 cohc = &base->chans[i];
1424 cohc->base = base;
1425 cohc->chan.device = dma;
1426 cohc->id = i;
1432 spin_lock_init(&cohc->lock);
1434 cohc->nbr_active_done = 0;
1435 cohc->busy = 0;
1436 INIT_LIST_HEAD(&cohc->free);
1437 INIT_LIST_HEAD(&cohc->active);
1438 INIT_LIST_HEAD(&cohc->queue);
1440 tasklet_init(&cohc->tasklet, dma_tasklet,
1441 (unsigned long) cohc);
1443 list_add_tail(&cohc->chan.device_node,