Lines Matching refs:cpu_to_be32
141 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
142 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
143 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
144 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
147 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
148 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
149 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
150 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
151 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
152 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
153 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
154 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
155 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
156 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
159 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
160 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
161 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
162 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
163 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
164 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
165 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
166 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
167 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
168 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
169 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
170 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
171 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
172 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
181 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
182 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
183 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
184 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
187 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
188 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
189 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
190 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
191 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
192 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
193 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
194 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
195 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
196 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
205 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
208 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
211 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
212 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
213 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
214 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)