Lines Matching refs:SCCwrite
231 SCCwrite(INT_AND_DMA_REG, 0);
233 SCCwrite(INT_VECTOR_REG, MVME147_IRQ_SCC_BASE);
235 SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);
267 SCCwrite(INT_AND_DMA_REG, 0);
337 SCCwrite(INT_AND_DMA_REG, 0);
339 SCCwrite(INT_VECTOR_REG, MVME162_IRQ_SCC_BASE);
341 SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);
373 SCCwrite(INT_AND_DMA_REG, 0);
440 SCCwrite(INT_AND_DMA_REG, 0);
442 SCCwrite(INT_VECTOR_REG, BVME_IRQ_SCC_BASE);
444 SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);
476 SCCwrite(INT_AND_DMA_REG, 0);
574 SCCwrite(COMMAND_REG, CR_ERROR_RESET);
597 SCCwrite(COMMAND_REG, CR_ERROR_RESET);
616 SCCwrite(COMMAND_REG, CR_TX_PENDING_RESET);
622 SCCwrite(TX_DATA_REG, port->x_char);
630 SCCwrite(TX_DATA_REG, port->gs.xmit_buf[port->gs.xmit_tail++]);
640 SCCwrite(COMMAND_REG, CR_TX_PENDING_RESET); /* disable tx_int on next tx underrun? */
674 SCCwrite(COMMAND_REG, CR_EXTSTAT_RESET);
828 SCCwrite(TIMER_LOW_REG, brgval & 0xff);
829 SCCwrite(TIMER_HIGH_REG, (brgval >> 8) & 0xff);
885 SCCwrite(TX_CTRL_REG, t);
975 SCCwrite(mvme_init_tab[i].reg, mvme_init_tab[i].val);
981 SCCwrite(bvme_init_tab[i].reg, bvme_init_tab[i].val);