Lines Matching refs:INT_AND_DMA_REG
231 SCCwrite(INT_AND_DMA_REG, 0);
267 SCCwrite(INT_AND_DMA_REG, 0);
337 SCCwrite(INT_AND_DMA_REG, 0);
373 SCCwrite(INT_AND_DMA_REG, 0);
440 SCCwrite(INT_AND_DMA_REG, 0);
476 SCCwrite(INT_AND_DMA_REG, 0);
615 SCCmod (INT_AND_DMA_REG, ~IDR_TX_INT_ENAB, 0);
639 SCCmod (INT_AND_DMA_REG, ~IDR_TX_INT_ENAB, 0);
691 SCCmod(INT_AND_DMA_REG, ~IDR_TX_INT_ENAB, 0);
704 SCCmod(INT_AND_DMA_REG, 0xff, IDR_TX_INT_ENAB);
718 SCCmod(INT_AND_DMA_REG,
731 SCCmod(INT_AND_DMA_REG, 0xff,
920 { INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },
949 { INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },