Lines Matching defs:set
299 u32 max_frame_size; /* as set by device config */
514 unsigned int set, unsigned int clear);
1389 * set or clear transmit break condition
1390 * break_state -1=set break condition, 0=clear
1417 * set encoding and frame check sequence (FCS) options
1648 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
2252 * is set to index of first unsent buffer
2286 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2886 * set general purpose IO pin state and direction
2890 * smask set bit indicates pin state to set
2892 * dmask set bit indicates pin direction to set
2992 * smask - set bit indicates watched pin
2995 * state. When 0 (no error) is returned, user_gpio->state is set to the
3017 /* ignore output pins identified by set IODR bit */
3129 * set modem control signals (DTR/RTS)
3131 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3132 * TIOCMSET = set/clear signal values
3136 unsigned int set, unsigned int clear)
3141 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3143 if (set & TIOCM_RTS)
3145 if (set & TIOCM_DTR)
3201 /* nonblock mode is set or port is not enabled */
3538 info->init_error = -1; /* assume error, set to 0 on successful init */
3806 /* set reset bit */
3819 /* set reset bit */
3849 /* set speed if available, otherwise use default */
3858 * set baud rate generator to specified rate
3885 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3910 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3927 /* set 1st descriptor address */
3979 /* set 1st descriptor address and start DMA */
3996 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4378 * set transmit idle mode
4390 /* disable preamble, set idle size to 16 bits */
4395 /* preamble is disabled, set idle size to 8 bits */
4440 * set V.24 Control Register based on current configuration
4482 * set state of V24 control (output) signals
4817 * set EOF bit for last buffer of HDLC frame or
4826 /* set descriptor count for all but first buffer */
4837 /* set first buffer count to make new data visible to DMA controller */