Lines Matching refs:BIT8
508 #define RXSTATUS_SHORT_FRAME BIT8
509 #define RXSTATUS_CODE_VIOLATION BIT8
570 #define MISCSTATUS_DSR BIT8
593 #define SICR_DSR_INACTIVE BIT8
594 #define SICR_DSR (BIT9+BIT8)
1651 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
4551 /* Note: must preserve state of BIT8 in DCAR */
4580 /* Note: must preserve state of BIT8 in DCAR */
4836 RegValue |= BIT9 + BIT8;
4838 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4993 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
4997 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5044 info->mbre_bit = BIT8;
5045 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5157 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5158 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5160 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
6107 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
7311 if ( status & (BIT8 + BIT3 + BIT1) ) {