Lines Matching refs:BIT1
500 #define IO_PIN BIT1
519 #define RXSTATUS_OVERRUN BIT1
557 #define TXSTATUS_UNDERRUN BIT1
577 #define MISCSTATUS_BRG1_ZERO BIT1
603 #define SICR_BRG1_ZERO BIT1
637 #define TXSTATUS_UNDERRUN BIT1
642 #define DICR_RECEIVE BIT1
1607 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
5228 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5291 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5429 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5432 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5518 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5521 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
6107 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6317 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
7270 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7285 if ( status & (BIT5 + BIT1) )
7311 if ( status & (BIT8 + BIT3 + BIT1) ) {