Lines Matching defs:io_base
264 unsigned int io_base; /* base I/O address of adapter */
1469 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1470 info->io_base + CCAR );
1471 DataByte = inb( info->io_base + CCAR );
3477 info->device_name, info->io_base, info->irq_level,
3481 info->device_name, info->io_base,
3553 u16 Ccar = inw( info->io_base + CCAR );
4073 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4075 __FILE__,__LINE__,info->device_name, info->io_base);
4174 release_region(info->io_base,info->io_addr_size);
4251 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4256 info->device_name, info->io_base, info->irq_level, info->dma_level,
4396 info->io_base = (unsigned int)io[i];
4499 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4503 inw( info->io_base + CCAR );
4524 outw( Cmd + info->mbre_bit, info->io_base );
4528 inw( info->io_base );
4553 outw( RegAddr + info->mbre_bit, info->io_base );
4554 outw( RegValue, info->io_base );
4558 inw( info->io_base );
4582 outw( RegAddr + info->mbre_bit, info->io_base );
4583 return inw( info->io_base );
4606 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4607 outw( RegValue, info->io_base + CCAR );
4611 inw( info->io_base + CCAR );
4631 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4632 return inw( info->io_base + CCAR );
5042 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5045 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5235 outw( 0x0300, info->io_base + CCAR );
5242 outw( 0,info->io_base + CCAR );
5712 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5719 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5720 info->io_base + CCAR );
5724 outw( info->x_char,info->io_base + CCAR );
5727 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5782 outb( 0,info->io_base + 8 );
5802 * By writing to io_base + SDPIN the Wait/Ack pin is
5806 outw( 0x000c,info->io_base + SDPIN );
5809 outw( 0,info->io_base );
5810 outw( 0,info->io_base + CCAR );
5865 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
6037 outw(0x0300, info->io_base + CCAR);
6099 outw(0,info->io_base + DATAREG);
7349 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
8005 dev->base_addr = info->io_base;
8063 info->io_base = pci_resource_start(dev, 2);