Lines Matching refs:sOutW
2527 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2649 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2704 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2706 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2835 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2836 sOutW(ChP->IndexData, 0);
2842 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2843 sOutW(ChP->IndexData, 0);
2844 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2845 sOutW(ChP->IndexData, 0);
2847 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2850 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2921 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2922 sOutW(ChP->IndexData, 0);
2923 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2924 sOutW(ChP->IndexData, 0);
2963 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2964 sOutW(ChP->IndexData, 0);
2991 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */