Lines Matching defs:ChP
234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237 static void sFlushRxFIFO(CHANNEL_T * ChP);
238 static void sFlushTxFIFO(CHANNEL_T * ChP);
239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
1149 static int sGetChanRI(CHANNEL_T * ChP)
1151 CONTROLLER_t *CtlP = ChP->CtlP;
1152 int ChanNum = ChP->ChanNum;
1158 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
2716 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2718 CHANNEL_T *ChP; Ptr to channel structure
2728 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2743 ChP->CtlP = CtlP;
2744 ChP->ChanID = CtlP->AiopID[AiopNum];
2745 ChP->AiopNum = AiopNum;
2746 ChP->ChanNum = ChanNum;
2750 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2751 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2752 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2753 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2754 ChP->IndexData = AiopIO + _INDX_DATA;
2757 ChIOOff = AiopIO + ChP->ChanNum * 2;
2758 ChP->TxRxData = ChIOOff + _TD0;
2759 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2760 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2761 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2769 out32(ChP->IndexAddr, R);
2772 ChR = ChP->R;
2788 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2789 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2790 ChP->BaudDiv[2] = (Byte_t) brd9600;
2791 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2792 out32(ChP->IndexAddr, ChP->BaudDiv);
2794 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2795 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2796 ChP->TxControl[2] = 0;
2797 ChP->TxControl[3] = 0;
2798 out32(ChP->IndexAddr, ChP->TxControl);
2800 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2801 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2802 ChP->RxControl[2] = 0;
2803 ChP->RxControl[3] = 0;
2804 out32(ChP->IndexAddr, ChP->RxControl);
2806 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2807 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2808 ChP->TxEnables[2] = 0;
2809 ChP->TxEnables[3] = 0;
2810 out32(ChP->IndexAddr, ChP->TxEnables);
2812 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2813 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2814 ChP->TxCompare[2] = 0;
2815 ChP->TxCompare[3] = 0;
2816 out32(ChP->IndexAddr, ChP->TxCompare);
2818 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2819 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2820 ChP->TxReplace1[2] = 0;
2821 ChP->TxReplace1[3] = 0;
2822 out32(ChP->IndexAddr, ChP->TxReplace1);
2824 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2825 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2826 ChP->TxReplace2[2] = 0;
2827 ChP->TxReplace2[3] = 0;
2828 out32(ChP->IndexAddr, ChP->TxReplace2);
2830 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2831 ChP->TxFIFO = ChOff + _TX_FIFO;
2833 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2834 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2835 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2836 sOutW(ChP->IndexData, 0);
2837 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2838 ChP->RxFIFO = ChOff + _RX_FIFO;
2840 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2841 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2842 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2843 sOutW(ChP->IndexData, 0);
2844 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2845 sOutW(ChP->IndexData, 0);
2846 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2847 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2848 sOutB(ChP->IndexData, 0);
2849 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2850 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2851 sOutB(ChP->IndexData, 0);
2852 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2853 sEnRxProcessor(ChP); /* start the Rx processor */
2861 Call: sStopRxProcessor(ChP)
2862 CHANNEL_T *ChP; Ptr to channel structure
2876 static void sStopRxProcessor(CHANNEL_T * ChP)
2880 R[0] = ChP->R[0];
2881 R[1] = ChP->R[1];
2883 R[3] = ChP->R[3];
2884 out32(ChP->IndexAddr, R);
2890 Call: sFlushRxFIFO(ChP)
2891 CHANNEL_T *ChP; Ptr to channel structure
2901 static void sFlushRxFIFO(CHANNEL_T * ChP)
2907 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2911 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2913 sDisRxFIFO(ChP); /* disable it */
2915 sInB(ChP->IntChan); /* depends on bus i/o timing */
2917 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2918 Ch = (Byte_t) sGetChanNum(ChP);
2919 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2920 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2921 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2922 sOutW(ChP->IndexData, 0);
2923 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2924 sOutW(ChP->IndexData, 0);
2926 sEnRxFIFO(ChP); /* enable Rx FIFO */
2932 Call: sFlushTxFIFO(ChP)
2933 CHANNEL_T *ChP; Ptr to channel structure
2943 static void sFlushTxFIFO(CHANNEL_T * ChP)
2949 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2953 if (ChP->TxControl[3] & TX_ENABLE) {
2955 sDisTransmit(ChP); /* disable transmitter */
2957 sStopRxProcessor(ChP); /* stop Rx processor */
2959 sInB(ChP->IntChan); /* depends on bus i/o timing */
2960 Ch = (Byte_t) sGetChanNum(ChP);
2961 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2962 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2963 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2964 sOutW(ChP->IndexData, 0);
2966 sEnTransmit(ChP); /* enable transmitter */
2967 sStartRxProcessor(ChP); /* restart Rx processor */
2973 Call: sWriteTxPrioByte(ChP,Data)
2974 CHANNEL_T *ChP; Ptr to channel structure
2983 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2989 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2990 IndexAddr = ChP->IndexAddr;
2991 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2992 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2996 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3001 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3008 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3016 Call: sEnInterrupts(ChP,Flags)
3017 CHANNEL_T *ChP; Ptr to channel structure
3045 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3049 ChP->RxControl[2] |=
3052 out32(ChP->IndexAddr, ChP->RxControl);
3054 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3056 out32(ChP->IndexAddr, ChP->TxControl);
3059 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3060 sOutB(ChP->IntMask, Mask);
3067 Call: sDisInterrupts(ChP,Flags)
3068 CHANNEL_T *ChP; Ptr to channel structure
3089 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3093 ChP->RxControl[2] &=
3095 out32(ChP->IndexAddr, ChP->RxControl);
3096 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3097 out32(ChP->IndexAddr, ChP->TxControl);
3100 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3101 sOutB(ChP->IntMask, Mask);
3105 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3107 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);