Lines Matching defs:io
252 static int sReadAiopID(ByteIO_t io);
253 static int sReadAiopNumChan(WordIO_t io);
2494 ByteIO_t io;
2514 io = AiopIOList[i];
2515 CtlP->AiopIO[i] = (WordIO_t) io;
2516 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2518 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2522 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2526 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2527 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2528 sOutB(io + _INDX_DATA, sClockPrescale);
2616 ByteIO_t io;
2640 io = AiopIOList[i];
2641 CtlP->AiopIO[i] = (WordIO_t) io;
2642 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2644 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2648 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2649 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2650 sOutB(io + _INDX_DATA, sClockPrescale);
2663 Call: sReadAiopID(io)
2664 ByteIO_t io: AIOP base I/O address
2671 static int sReadAiopID(ByteIO_t io)
2675 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2676 sOutB(io + _CMD_REG, 0x0);
2677 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2688 Call: sReadAiopNumChan(io)
2689 WordIO_t io: AIOP base I/O address
2697 static int sReadAiopNumChan(WordIO_t io)
2703 out32((DWordIO_t) io + _INDX_ADDR, R);
2704 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2705 x = sInW(io + _INDX_DATA);
2706 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2707 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */