Lines Matching refs:x80
117 #define RCSR_TOUT 0x80 /* Rx Timeout */
134 #define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
157 #define IER_DSR 0x80 /* Enable interrupt on DSR change */
169 #define COR1_ODDP 0x80 /* Odd Parity */
188 #define COR2_IXM 0x80 /* Implied XON mode */
200 #define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
209 #define CCSR_RXEN 0x80 /* Receiver Enabled */
219 #define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
228 #define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
235 #define MCR_DSRCHG 0x80 /* DSR Changed */
242 #define MSVR_DSR 0x80 /* Current state of DSR input */