Lines Matching defs:DBG1
81 #define DBG1(args...) D_(0x01, ##args)
118 DBG1("SENDING: '%s' (%d+n)", tbuf, len__);\
120 DBG1("SENDING: '%s' (%d)", tbuf, len__);\
675 DBG1("Second phase, configuring card");
682 DBG1("toggle ports: MDM UL:%d MDM DL:%d, DIAG DL:%d",
705 DBG1("First phase: pushing upload buffers, clearing download");
726 DBG1("First phase done");
834 DBG1("tty not open for port: %d?", index);
839 /* DBG1( "%d bytes port: %d", size, index); */
842 DBG1("No room in tty, don't read data, don't ack interrupt, "
941 DBG1("The Base Band sends this value as a response to a "
975 DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
982 DBG1("Disable interrupt (0x%04X) on port: %d",
989 DBG1("Enable interrupt (0x%04X) on port: %d",
991 DBG1("Data in buffer [%d], enable transmit! ",
995 DBG1("No data in buffer...");
1000 DBG1(" No change in mctrl");
1015 DBG1("port: %d DCD(%d), CTS(%d), RI(%d), DSR(%d)",
1209 DBG1("CTRL_UL");
1458 DBG1("base_addr: %p", dc->base_addr);
1515 DBG1(" ");
1552 DBG1("sending flow control 0x%04X", *((u16 *)&ctrl));
1591 DBG1("SETTING DTR index: %d, dtr: %d", tty->index, dtr);
1632 DBG1("open: %d", port->token_dl);
1654 DBG1("close: %d", port->token_dl);
1688 /* DBG1( "WRITEx: %d, index = %d", count, index); */
1696 DBG1(" ");
1704 DBG1("No device context?");
1834 DBG1("******** IOCTL, cmd: %d", cmd);
1847 DBG1("ERR: 0x%08X, %d", cmd, cmd);
1863 DBG1("UNTHROTTLE");
1880 DBG1("THROTTLE");