Lines Matching defs:mmr_base
204 void *mmr_base;
209 mmr_base = soft->mmr_base;
220 mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
234 cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
236 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
244 void *mmr_base;
249 mmr_base = soft->mmr_base;
260 mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
274 cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
276 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
285 void *mmr_base = soft->mmr_base;
293 mbcs_algo_set(mmr_base,
300 cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
303 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
484 uint64_t mmr_base;
486 mmr_base = (uint64_t) (soft->mmr_base + offset);
488 return mmr_base;
532 void *mmr_base;
536 mmr_base = soft->mmr_base;
537 cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
542 MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
544 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
552 MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
554 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
562 MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
564 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
672 void *mmr_base = soft->mmr_base;
678 MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
681 MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
688 err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
689 MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
690 MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
694 MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
697 cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
703 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
765 soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);